Dual Fin Endcap Self-Aligned Gate Edge Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices faces challenges due to constraints in lithographic processes, particularly in achieving the optimal spacing and dimensions of gate endcaps, which affects transistor density and performance, as conventional methods require extra endcap length for mask registration error and result in increased gate capacitance and energy consumption.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architecture, where a disposable spacer on semiconductor fin edges determines the gate and trench contact endcap dimensions, eliminating the need for extra endcap length to account for mask registration errors and allowing for fixed dimensions without lithographic patterning, thereby reducing device variability and enabling more aggressive scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to define gate endcaps, then mask registration errors require extra endcap length, but this increases gate capacitance and energy consumption
Solution Approach 1:
The gate endcap structure performs self-alignment through the formation sequence where the gate electrode automatically defines the endcap boundaries. The disposable spacer is positioned relative to the gate electrode, and the endcap is formed by removing the spacer material adjacent to the gate, allowing the gate structure itself to serve as the alignment reference rather than requiring separate lithographic patterning steps
Solution Approach 2:
The patent extracts the alignment function from the lithographic patterning process and transfers it to the gate electrode structure itself. By removing the dependency on lithographic mask registration, the design eliminates the need for extra endcap length that was previously required to compensate for mask alignment errors
2Manufacturing precision
If extra endcap length is added to account for mask registration errors, then alignment tolerance is improved, but transistor density decreases
Solution Approach 1:
The self-aligned endcap formation process uses the gate electrode structure itself as the reference for defining endcap boundaries. The disposable spacer is positioned relative to the gate, and selective removal of spacer material creates the endcap region. This self-referencing approach eliminates alignment tolerance requirements while maintaining minimum endcap dimensions for electrical performance
Solution Approach 2:
The patent changes the critical parameter from lithographic pattern dimensions to deposited layer thicknesses. The endcap length is determined by the thickness of the disposable spacer layer and the selective removal process, rather than by lithographic patterning dimensions. This parameter change enables precise control without requiring alignment tolerance
3Adaptability or versatility
If lithographic patterning is used for endcap definition, then process flexibility is maintained, but device variability increases
Solution Approach 1:
The patent replaces the mechanical lithographic patterning system with a deposition and selective removal system. Instead of using lithographic masks and etching to define endcaps, the process uses conformal deposition of disposable spacer material followed by selective removal adjacent to the gate electrode. This substitution eliminates variability introduced by lithographic alignment and etching uniformity
Solution Approach 2:
The critical dimension control transitions from lithographic parameters (wavelength, numerical aperture, resist properties) to deposition parameters (film thickness, conformality) and etch parameters (selectivity, anisotropy). This parameter change reduces device variability by using processes with better uniformity and control
Data Source
AI summary
Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.