Dual Fin Single Floating Gate Flash Memory Scalability
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Solution Overview
Problem
Current flash memory devices face limitations in scaling due to the inability to increase the amount of electrical charge stored in floating gates, and they are being replaced by fin field effect transistors in advanced logic circuitry, necessitating a scalable flash memory device based on fin field effect transistors.
Innovation Solution
A flash memory device is developed using a dual fin single floating gate configuration, where semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer, with a floating gate electrode deposited between pairs of semiconductor fins and a control gate structure formed on top, enabling efficient charge storage and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional planar floating gate structures are used, then manufacturing is simpler, but scalability is limited due to inability to increase charge storage capacity
Solution Approach 1:
The patent transitions from planar 2D floating gate structures to 3D vertical fin-based structures. Multiple fins are formed vertically, with tunneling dielectrics deposited on fin sidewalls and floating gate electrodes formed between fin pairs. This vertical dimensionality multiplication enables increased charge storage capacity while maintaining planar process compatibility, directly resolving the scalability limitation of conventional devices.
Solution Approach 2:
The floating gate storage function is segmented across multiple discrete fin structures rather than relying on a single large planar gate. Each fin pair with its associated tunneling dielectric and floating gate electrode constitutes an independent storage unit. This segmentation enables scalable expansion of total storage capacity by increasing fin density or adding more fin pairs, while each individual unit maintains manufacturability.
2Adaptability or versatility
If fin field effect transistor structure is adopted, then scalability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The fin structures serve as self-aligned templates for subsequent processing steps. Tunneling dielectric deposition on fin sidewalls and floating gate electrode formation between fin pairs are performed using the fins themselves as alignment references, eliminating the need for separate lithography alignment steps. This self-service approach reduces manufacturing precision requirements while enabling the complex 3D fin-based structure.
Solution Approach 2:
The fin structures are formed first as preliminary elements that define the geometry for all subsequent processing. The tunneling dielectric is deposited conformally on pre-formed fin sidewalls, and floating gate electrodes are formed in pre-defined spaces between fin pairs. This preliminary fin formation establishes the structural framework that guides all subsequent self-aligned processing steps, reducing overall manufacturing precision demands.
3Quantity of substance
If dual fin single floating gate configuration is used, then charge storage efficiency is improved, but device complexity increases
Solution Approach 1:
Two separate fin structures are merged to share a single floating gate electrode between them. The floating gate electrode is formed in the space between the fin pairs and electrically connects to both fins through the tunneling dielectric interface. This merging configuration doubles the effective charge storage capacity per unit area compared to single-fin structures, while the shared floating gate reduces overall device complexity by eliminating redundant gate structures.
Data Source
AI summary
A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.