Dual Fin Structures for Gate Control and Leakage Reduction
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Solution Overview
Problem
The short channel effect in silicon-based CMOS transistors, where decreasing channel lengths lead to degraded gate control, reduced threshold voltage, and decreased drive current, poses challenges in maintaining performance as device dimensions shrink.
Innovation Solution
The method involves fabricating semiconductor device structures with dual fins, using a process that includes forming a mask layer, patterning it to create apertures, forming trenches with sloped or angled sidewalls, and depositing dielectric material to isolate the fins, which are then further isolated using spade and bowl etches to reduce cross-talk and leakage current, ultimately forming dual fin structures that enhance gate control and drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is reduced to increase operation speed and component density, then productivity and speed improve, but gate control deteriorates and short channel effects increase
Solution Approach 1:
The semiconductor structure is divided into multiple fins instead of a single planar channel. The dual-fin configuration segments the current path and increases the effective gate control area, allowing better electrostatic control even at reduced channel lengths
Solution Approach 2:
The invention transitions from a two-dimensional planar channel to a three-dimensional vertical fin structure. This dimensional change increases the surface area available for gate control while maintaining a short horizontal channel length, thus improving gate control without sacrificing speed
2Area of stationary object
If channel length is reduced to increase component density, then area utilization improves, but threshold voltage control deteriorates
Solution Approach 1:
The channel is segmented into multiple fins, increasing the effective channel width and allowing higher component density while maintaining adequate gate control through the increased surface area
Solution Approach 2:
The invention changes the geometric parameters by creating vertical fins with controlled heights and spacing. This allows the threshold voltage to be controlled through the fin dimensions and doping profiles while maintaining high component density
3Speed
If source and drain regions are extended towards each other to reduce channel length, then speed increases, but cross-talk and leakage current increase
Solution Approach 1:
The dual-fin structure segments the source and drain regions, reducing direct interaction between them. The increased vertical separation and staggered configuration minimize cross-talk and leakage current while maintaining short horizontal channel length for high speed
Solution Approach 2:
By transitioning to vertical fins, the invention increases separation in the vertical dimension while maintaining short horizontal channels. This dimensional change reduces parasitic effects and leakage paths between source and drain
Data Source
AI summary
Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.