Dual-Fin Transistor Structure with Shared Metal Gate
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Solution Overview
Problem
The miniaturization of integrated circuits (ICs) has led to challenges in maintaining efficient power consumption and performance, particularly in the design and manufacturing of logic cells, where the integration of transistors and gate structures affects circuit speed and power consumption.
Innovation Solution
The semiconductor structure incorporates dual-fin FETs with dielectric-base dummy gates and shared metal gate electrodes, along with specific transistor configurations and doping materials, to optimize transistor performance and reduce capacitance between contacts, thereby improving circuit speed and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are miniaturized to increase integration density, then device functionality and power efficiency are improved, but capacitance between contacts increases and circuit speed deteriorates
Solution Approach 1:
The transistor channel is segmented into dual-fins, creating separate current paths that reduce the overall capacitance between contacts while maintaining high integration density. The dual-fin structure divides the channel region into distinct segments that can be independently controlled, thereby improving circuit speed despite miniaturization.
Solution Approach 2:
The patent transitions from a planar transistor structure to a three-dimensional dual-fin configuration. This dimensional change increases the effective channel area and integration density while the vertical fin structure reduces the horizontal distance between contacts, thereby reducing capacitance and improving circuit speed.
2Quantity of substance
If transistors are miniaturized to increase integration density, then device functionality is improved, but power consumption increases
Solution Approach 1:
The dual-fin structure segments the channel into separate regions that can be independently controlled by adjacent gates. This segmentation reduces the total capacitance between contacts, thereby reducing the energy required for charging and discharging operations and lowering overall power consumption while maintaining high integration density.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by introducing dual-fins with specific width and spacing dimensions. These parameter changes optimize the balance between integration density and power consumption by reducing capacitance effects that would otherwise increase power requirements in miniaturized devices.
3Speed
If dual-fin structure with shared gates is used, then capacitance between contacts is reduced and circuit speed is improved, but device complexity increases
Solution Approach 1:
Adjacent transistors share common gate electrodes, merging the gate control function into a single structure that controls multiple fin regions. This merging reduces the total number of separate gate components needed, thereby reducing device complexity while the dual-fin structure itself reduces capacitance and improves circuit speed.
Data Source
AI summary
Semiconductor structures are provided. Each transistor includes a first source/drain region over a semiconductor fin, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction. In a first transistor of the transistors, the first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors. The second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate. A first contact of the first source/drain region is separated from a spacer of the metal gate electrode of the first transistor. A second contact of the second source/drain region is in contact with a spacer of the dielectric-base dummy gate.