Dual Fixed Geometry FFT Architecture for Wireless Signal Processing
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Solution Overview
Problem
The bit-reversal stage in radix-2 FFT operations is a bottleneck for processors in wireless devices, consuming resources and battery life due to individual data handling and requiring additional computation cycles.
Innovation Solution
Implementing dual fixed geometry FFT operations without a dedicated bit-reversal stage by using a common data processing path with either a shuffle input/output network or a deal input/output network, allowing for bit-reversal operations within the existing data processing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a dedicated bit-reversal stage is implemented in radix-2 FFT operations, then the FFT output can be produced in normal order, but the processing resources are strained and battery life is consumed
Solution Approach 1:
The patent merges the bit-reversal operation with the existing FFT computation stages by using a dual fixed-geometry architecture. The same computational units perform both the FFT calculations and the bit-reversal reordering operations, eliminating the need for a separate dedicated bit-reversal stage. This integration reduces overall processing cycles and energy consumption while maintaining normal order output capability.
Solution Approach 2:
The dual fixed-geometry FFT architecture implements multi-functional computational units that can perform both FFT computation and bit-reversal operations. The first and second FFT engines share common resources and can be configured to execute different geometries, allowing the system to handle both computation and reordering tasks within the same hardware structure, thereby reducing resource strain and power consumption.
2Ease of operation
If a dedicated bit-reversal stage is implemented, then data can be reordered to normal order, but the system complexity increases
Solution Approach 1:
The patent combines the bit-reversal functionality with the existing FFT computational structure. Instead of adding a separate reordering stage, the system uses the dual fixed-geometry architecture to perform bit-reversal as part of the computation process itself, thereby achieving data reordering without increasing overall system complexity.
Solution Approach 2:
The dual fixed-geometry FFT implementation allows dynamic configuration of the computational units to perform different operations. The same hardware structure can be adapted to execute either FFT computation or bit-reversal operations depending on the required geometry, providing flexibility without requiring additional dedicated hardware for each function.
3Manufacturing precision
If individual data handling is used in bit-reversal stage, then precise reordering can be achieved, but execution time increases
Solution Approach 1:
The patent merges bit-reversal operations with FFT computation stages, allowing precise data reordering to occur concurrently with mathematical calculations. This eliminates sequential processing delays and reduces total execution cycles while maintaining accurate reordering through the integrated dual-geometry architecture.
Solution Approach 2:
The dual fixed-geometry implementation enables continuous processing where bit-reversal operations are performed alongside FFT computations rather than as a separate post-processing step. This continuous action approach maintains data reordering accuracy while minimizing idle time and reducing overall execution duration.
Data Source
AI summary
A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.