Dual-Flag Stacked Die Package for MOSFET Reliability
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Solution Overview
Problem
The challenge lies in packaging multiple semiconductor integrated circuits in a single package with improved manufacturability and reliability, particularly in achieving a smaller footprint while addressing issues such as uncontrollable movement during board mounting and mold flow problems caused by large single die flags.
Innovation Solution
A dual flag stacked die package design where two MOSFET die are placed on separate flags with a gap between them, allowing for improved board mounting and mold compound flow, and a power control IC is stacked on top, using thinner die to reduce overall package thickness and enhance electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large single die flag is used to accommodate two MOSFETs, then the turn-on resistance is minimized, but the package becomes difficult to board mount and experiences uncontrollable movement
Solution Approach 1:
The patent divides the single large die flag into two separate die flags, each supporting one MOSFET die. This segmentation prevents the package from floating uncontrollably during board mounting while maintaining electrical performance through proper flag sizing and configuration.
2Reliability
If a large single die flag is used, then electrical performance is maintained, but mold flow problems and reliability issues occur
Solution Approach 1:
The single large die flag is segmented into two separate die flags with individual MOSFET die. This resolves mold flow imbalances and reliability issues associated with large single flags while maintaining necessary electrical connections through the lead frame structure.
Solution Approach 2:
The patent transitions from a planar single-flag configuration to a three-dimensional stacked die architecture where MOSFET die are vertically positioned on separate flags, allowing improved mold flow characteristics and reduced packaging footprint.
3Area of stationary object
If multiple die are stacked to reduce footprint, then package size is minimized, but manufacturing challenges and reliability risks increase
Solution Approach 1:
The patent employs vertical stacking of MOSFET die on separate die flags in the z-dimension, achieving reduced package footprint while maintaining manufacturability through standardized die attach processes and proper flag design that prevents manufacturing challenges.
Solution Approach 2:
Each die flag is independently optimized for its specific MOSFET die, allowing local quality control in the stacking arrangement. This approach maintains manufacturing ease by enabling independent die attach processes while achieving compact footprint through vertical integration.
4Ease of operation
If a large single die flag is used, then electrical connections are simplified, but alignment control during mounting deteriorates
Solution Approach 1:
The single large die flag is divided into two separate die flags, each providing stable support for individual MOSFET die. This segmentation improves alignment control during board mounting by eliminating the floating effect while maintaining electrical connections through the lead frame's interconnected structure.
Data Source
AI summary
In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags.