Shared-Clock Dual Flip-Flop Circuit for Lower Clock Tree Power
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Solution Overview
Problem
The increasing power consumption of clock trees in integrated circuits, particularly in portable devices, due to the growing load presented by clocked circuits, necessitates a solution to manage this load effectively.
Innovation Solution
A dual flip-flop circuit is introduced, combining two or more flip-flop sub-circuits into a single circuit with a shared clock driver and scan enable buffer, reducing the load on the clock signal and power consumption by halving the number of clock signals generated by the clock tree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of buffers in the clock tree is increased to manage the load presented by clocked circuits, then the timing characteristics of the clock signal are maintained, but the power consumption of the clock tree increases
Solution Approach 1:
The patent combines multiple flip-flop sub-circuits into a single dual flip-flop circuit that shares a common clock driver. This merging reduces the total number of clock drivers and buffers required in the clock tree, thereby reducing power consumption while maintaining proper timing characteristics through the shared clock distribution infrastructure
Solution Approach 2:
The shared clock driver in the dual flip-flop circuit serves multiple functions by providing clock signals to both flip-flop sub-circuits simultaneously. This multi-functionality reduces the overall number of clock drivers needed in the system, decreasing power consumption without compromising the timing requirements of individual flip-flops
2Use of energy by stationary object
If two or more flip-flop sub-circuits are combined into a single dual flip-flop circuit with a shared clock driver, then the power consumption and die area are reduced, but the device complexity increases
Solution Approach 1:
The patent merges multiple flip-flop sub-circuits into a single integrated dual flip-flop circuit with shared clock driver and scan enable buffer. This consolidation reduces the overall device complexity by eliminating redundant components while maintaining individual flip-flop functionality, thereby reducing both power consumption and die area
Data Source
AI summary
A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.