Dual Floating Gate Deposit for NVM Capacitance
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Solution Overview
Problem
Existing non-volatile memory (NVM) devices face challenges in increasing the gate coupling factor due to the trade-off between capacitance between the control gate and floating gate, and the substrate, where reducing substrate capacitance is necessary to enhance performance without compromising data integrity.
Innovation Solution
A dual floating gate deposit method is employed, where a recess is formed in the shallow trench isolation region, allowing the floating gate to extend into the recess with a thick STI region separating it from the substrate, thereby increasing capacitance between the floating and control gates while minimizing substrate capacitance, using multiple deposition and etching steps to achieve a high gate coupling factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate oxide is made thinner to increase capacitance between floating gate and control gate, then the capacitance increases, but tunneling current arises causing data loss
Solution Approach 1:
The patent changes the physical parameters of the gate structure by introducing a recess in the gate oxide layer, allowing the floating gate to extend closer to the control gate. This geometric parameter change increases capacitance without requiring the gate oxide to be thinner, thereby avoiding tunneling current while achieving higher capacitance between floating gate and control gate.
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional structure with a recess. By extending the floating gate vertically into the recess, the patent increases the surface area and proximity between floating gate and control gate, achieving higher capacitance through dimensional change rather than reducing oxide thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the gate coupling factor and performance of NVM devices by optimizing capacitance ratios without increasing device area and maintaining data integrity.
Implementation Method 1
a gate dielectric layer located over the floating gate
Implementation Method 2
the capacitance between the control gate and the floating gate, and the capacitance between the floating gate and the substrate
Data Source
AI summary
A device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an STI material, and further comprising a recess in the STI material, the recess having a bottom and sides; a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by a portion of the STI material; and a gate dielectric layer located over the floating gate, and a control gate located over the gate dielectric layer, wherein a portion of the control gate is located in the recess.