Nonvolatile Memory Cell With Dual Floating Gates And N-Type Connection Region
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Solution Overview
Problem
Existing nonvolatile memory technologies face challenges in efficiently storing and retrieving two bits of information per memory cell due to limitations in channel resistance and electrical field distribution between floating gates, leading to issues like punch-through and short channel effects.
Innovation Solution
The introduction of two floating gates with an N-type connection region between them, which reduces channel resistance and can be programmed using hot hole or channel hot electron injection, and erased by Fowler-Nordheim tunneling, allowing for improved electrical field management and reduced punch-through risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single floating gate is used in each memory cell, then the device structure is simple, but the memory cell can only store one bit of information
Solution Approach 1:
The single floating gate is segmented into two separate floating gates (first floating gate and second floating gate) within each memory cell. This segmentation allows each gate to independently store one bit of information, enabling the memory cell to store two bits total while maintaining a relatively simple device structure that is an extension of the conventional single-floating-gate design
2Force
If the inter-gate dielectric is made thin to allow strong electrical field induction by wordlines, then the electrical field between floating gates is strong, but punch-through occurs between adjacent floating gates
Solution Approach 1:
An inter-gate dielectric layer is introduced as an intermediary between the first and second floating gates. This dielectric layer has a specific thickness range (50-200 nm) that allows it to mediate between the need for strong electrical field induction and the need to prevent punch-through, providing electrical isolation while still permitting sufficient field coupling for operation
3Reliability
If the channel region has high resistance, then the memory cell has good isolation, but the channel resistance between adjacent bitlines is too high for effective operation
Solution Approach 1:
The channel region is given different doping characteristics at different locations: it has higher resistance in regions providing cell isolation and lower resistance in regions between adjacent bitlines. This local variation in electrical properties allows the channel to simultaneously provide good isolation where needed and low resistance for effective bitline operation where needed
4Area of stationary object
If floating gates are placed close together to increase storage density, then the memory array density increases, but the electrical field distribution becomes problematic causing punch-through
Solution Approach 1:
The inter-gate dielectric serves as a mediator that enables close spacing of floating gates for increased density while maintaining proper electrical field distribution. The specific thickness range of the dielectric allows sufficient field coupling for operation while preventing direct punch-through between adjacent floating gates
Solution Approach 2:
The electrical field distribution is controlled by adjusting the inter-gate dielectric thickness parameter within a specific range (50-200 nm). This parameter optimization allows the system to achieve high density with close gate spacing while maintaining reliable electrical field distribution and preventing punch-through effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables each memory cell to store two bits of information effectively, with reduced channel resistance and minimized punch-through risks, enhancing the memory array's operational efficiency and reliability.
Implementation Method 1
The connection regions reduce the channel resistance between the adjacent bitlines
Implementation Method 2
Each floating gate can be programmed by hot hole injection ('HH injection')
Implementation Method 3
Each floating gate can be programmed by hot hole injection ('HH injection') or channel hot electron injection (CHEI)
Implementation Method 4
The cells can be erased by Fowler-Nordheim (FN) tunneling
Data Source
AI summary
A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.