Dual-Format Nonvolatile Memory Storage with On-Chip Latch Backup
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional nonvolatile memory systems face challenges in efficiently and accurately storing data due to higher error rates in higher density formats, which can lead to data corruption and require additional error correction mechanisms.
Innovation Solution
Implementing a dual-format storage system where data is written in both Single Level Cell (SLC) and Multi Level Cell (MLC) formats, with SLC serving as a backup to MLC, allowing for post-write reads to verify data integrity and ensure accurate storage, and using on-chip latches to manage and transfer data efficiently between formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher density storage format (MLC) is used, then storage capacity is improved, but error rate increases
Solution Approach 1:
The patent creates a backup copy of data in SLC format when MLC format is detected to have high error rate. The system writes the same data to both MLC and SLC memory regions, then uses the SLC copy as a fallback when MLC data proves corrupted or erroneous, thereby maintaining data integrity while utilizing high-capacity MLC storage.
Solution Approach 2:
The patent dynamically changes the storage format parameter based on error rate detection. When error rate exceeds a threshold, the system transitions from using only MLC format to using SLC format for backup or alternative storage, effectively adapting the storage parameters to maintain reliability while preserving capacity benefits.
2Reliability
If data is written in both SLC and MLC formats, then data integrity is improved, but write operation time increases
Solution Approach 1:
The patent implements partial dual-format writing by initially writing data only to MLC format. The SLC backup write is conditionally performed only when error correction fails or error rate is high, rather than always writing to both formats. This reduces the average write time while maintaining data integrity through selective backup creation.
Solution Approach 2:
The patent performs preliminary error detection after MLC write operations before committing to full dual-format storage. By first writing to MLC and then checking for errors, the system only invokes the time-consuming SLC backup write when necessary, rather than always performing both writes in advance.
3Measurement precision
If error correction mechanisms are added, then data accuracy is improved, but system complexity increases
Solution Approach 1:
The patent uses SLC memory as an intermediary backup storage layer between MLC storage and the error correction logic. Instead of implementing complex real-time error correction algorithms, the system simply writes backup copies to SLC and compares them when errors are detected, using the backup data as a mediator to restore accuracy without requiring sophisticated correction mechanisms.
4Manufacturing precision
If post-write verification is performed, then storage accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent implements selective verification by skipping the SLC backup write operation when MLC write succeeds without errors. The system rushes through the write process using only MLC format when conditions permit, and only performs the additional verification and backup write when error detection triggers the fallback mechanism, thereby maintaining speed when possible and accuracy when needed.
Data Source
AI summary
Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. High error rate format may be MLC format and programming in the high error rate format may program both lower page and upper page data together in a full sequence programming scheme that is suitable for handling high data volume.