Dual FPGA Accelerator Circuit Configuration Validation
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Solution Overview
Problem
Direct writing of a new arithmetic circuit into an FPGA accelerator can lead to operational issues if not properly configured, resulting in the accelerator not functioning normally.
Innovation Solution
A computing system with two computers, one writing an arithmetic circuit into a reconfigurable region of an FPGA accelerator and another writing the same circuit into a similar region of a second FPGA accelerator, with the second computer writing to an unwritten region if the first computer's write is unsuccessful, ensuring the circuit is properly configured and operational.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a new arithmetic circuit is directly written into the FPGA accelerator, then the processing capability is improved, but the reliability deteriorates because the accelerator may not operate normally if the circuit is not properly configured
Solution Approach 1:
The patent applies preliminary action by having the second computer write the arithmetic circuit into the second accelerator region in advance, before the first computer writes it into the first accelerator region. This pre-writing and validation approach ensures that the circuit configuration is verified beforehand, preventing operational failures in the primary accelerator.
Solution Approach 2:
The second accelerator region acts as an intermediary for validating arithmetic circuit configurations. Instead of directly writing into the primary accelerator, the system uses the second accelerator as a mediator to test and verify the circuit first, thereby protecting the primary accelerator from potential configuration errors.
2Adaptability or versatility
If the arithmetic circuit is written into the first accelerator region, then the system functionality is improved, but the risk of operational failure increases if the writing process encounters errors
Solution Approach 1:
The patent implements beforehand cushioning by preparing the second accelerator region with the same circuit arrangement as a backup and validation target. If the first accelerator region encounters writing errors or operational failures, the system can fall back to the pre-configured second region, cushioning against the harmful effects of operational failures.
Solution Approach 2:
The system creates a copy of the arithmetic circuit configuration in the second accelerator region, which has the same circuit arrangement as the first region. This copying approach allows validation and backup, reducing the risk of operational failure in the primary accelerator.
3Manufacturing precision
If the second computer writes to the same position as unwritten regions of the first region, then the configuration consistency is improved, but the complexity of coordinating between two computers increases
Solution Approach 1:
The patent applies local quality by having the second computer write the arithmetic circuit specifically into the same positional regions that are unwritten in the first accelerator region. This localized writing approach ensures configuration consistency only where needed, rather than duplicating entire circuits, thereby reducing unnecessary coordination complexity.
Data Source
AI summary
A computing system includes a first computer for writing an arithmetic circuit in a reconfigurable first region included in a first accelerator and a second computer for writing the arithmetic circuit in a reconfigurable second region included in a second accelerator different from the first accelerator and having the same circuit arrangement as the first region. When the first computer writes a new arithmetic circuit in the first region, the second computer writes the new arithmetic circuit in a partial region of the second region at the same position as the unwritten partial region of the first region. The first computer does not write the new arithmetic circuit in the first region when the new arithmetic circuit is not normally written, and writes the new arithmetic circuit in the unwritten partial region of the first region when the new arithmetic circuit is normally written.