Communication Processing Device with Dual FPGA Circuits for Seamless Protocol Updates
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Solution Overview
Problem
Existing communication processing devices struggle with synchronizing communication protocol processes between multiple FPGAs, leading to incorrect communication and high costs due to the need for multiple FPGAs, which are not addressed by existing solutions.
Innovation Solution
A communication processing device with a programmable logic device that includes two communication processing circuits, where one circuit operates while the other is updated, allowing for seamless switching and configuration of the second circuit using logic circuit data downloaded from the network, with a flag to indicate completion and a register for switching control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If multiple FPGAs are provided to enable protocol updates, then communication continuity is maintained, but device cost increases
Solution Approach 1:
The single FPGA is segmented into two functional parts: a first communication processing circuit that handles current communication protocols, and a second communication processing circuit that is being configured with updated protocols. This segmentation allows protocol updates without requiring multiple complete FPGA devices, thus maintaining communication continuity while reducing device cost.
Solution Approach 2:
The second communication processing circuit is preliminarily configured with updated protocol logic while the first circuit continues to handle communication. This preliminary action allows the system to prepare for protocol updates in advance without interrupting ongoing communications, and switch to the updated circuit once configuration is complete.
2Adaptability or versatility
If FPGAs perform discrete switching between circuits, then protocol updates are enabled, but communication correctness deteriorates due to lack of synchronization
Solution Approach 1:
A synchronization mechanism with feedback is implemented where the first communication processing circuit notifies the second circuit when communication pauses are detected. This feedback allows the second circuit to complete its configuration and switching preparation in sync with the communication flow, ensuring that both transmitting and receiving ends switch protocols simultaneously, thus maintaining communication correctness.
Solution Approach 2:
A synchronization intermediary mechanism is introduced that coordinates the switching actions between multiple FPGAs. This intermediary ensures that all communication processing devices in the network switch to updated protocols at the same time, preventing protocol mismatches between transmitting and receiving ends and ensuring communication correctness.
3Reliability
If communication protocol processes are updated, then security against cyberattacks is improved, but communication interruption occurs during the update process
Solution Approach 1:
The updated communication protocol logic is preliminarily configured in the second communication processing circuit before the first circuit is taken offline. This preliminary configuration ensures that when switching occurs, the updated protocol is already ready and validated, allowing security updates to be applied without communication interruption.
Solution Approach 2:
A standby communication processing circuit is prepared in advance with updated protocol logic, serving as a cushion or backup. This beforehand preparation ensures that if the update process encounters issues, the system can switch to the prepared circuit without interrupting communication, thus maintaining both security and continuity.
Data Source
AI summary
Provided are a communication processing device and a communication system, capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication. A communication processing device, which is connected to a communication network, includes a programmable logic device in which partial rewriting of a logic circuit is possible, during an operation of a host device in the communication network, in which the programmable logic device includes at least two communication processing circuits of which each performs a communication protocol process, and in which one communication processing circuit is operable due to switching, a first communication processing circuit performs communication, and a second communication processing circuit is on standby, updating means for downloading logic circuit data of an updated communication protocol process, from the communication network, and performing a circuit configuration for the second communication processing circuit, a flag that indicates whether or not the circuit configuration for the second communication processing circuit is finished, and by which a circuit configuration state is able to be read to the host device side through communication, and a register that is intended for switching to any one communication processing circuit to be used, and is writable from the host device side through communication.