Dual-Frequency Memory Module for Hierarchical Bus Interleaving
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Solution Overview
Problem
Standardized memory modules optimized for low-end systems are inefficient when used in larger systems, leading to potential losses in efficiency and increased costs due to the need for custom designs to meet different system requirements.
Innovation Solution
A memory module with dual bus frequency interfaces allows for daisy-chaining of memory chips in a hierarchical tree configuration, enabling efficient operation in both low-end and high-capacity systems by reducing bus frequency and I/O ports, and supporting interleaved data storage across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standardized memory modules optimized for low-end systems are used in larger systems, then cost is reduced and manufacturing simplicity is improved, but system performance and efficiency deteriorate
Solution Approach 1:
The memory chip is designed with dynamic operational modes that can adapt to different system requirements. The chip can operate in a first mode optimized for low-end systems with standardized interfaces, and in a second mode optimized for high-capacity systems with custom interfaces, allowing a single standardized module to deliver appropriate performance for each context without requiring different manufacturing processes
Solution Approach 2:
The invention changes operational parameters within the standardized memory chip to achieve different performance levels. By modifying bus frequency, data width, and operational timing parameters, the same standardized hardware can deliver differentiated performance characteristics suitable for both low-end and high-capacity systems without requiring custom manufacturing
2Productivity
If custom memory chip designs are used to meet different system requirements, then system performance and efficiency are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The standardized memory chip is designed with multi-functionality to serve multiple system types. It incorporates universal interfaces and configurable operational modes that allow it to function effectively in both standardized low-end systems and customized high-capacity systems, eliminating the need for separate custom-designed chips while maintaining high performance through software-controlled parameter adjustment
3Speed
If high bus frequency is used to maintain performance, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The memory chip implements dynamic frequency scaling that adjusts bus operating frequency based on actual system needs. The chip can operate at high frequencies when performance is required and automatically reduce to lower frequencies during normal operation, thereby maintaining data transfer speed when necessary while minimizing power consumption during typical workloads
Solution Approach 2:
The system employs periodic high-speed data transfers interspersed with lower-speed operations. By concentrating data transfer activities in periodic bursts at high frequency and using lower frequency for command and control operations, the system achieves high overall throughput while averaging lower power consumption across the complete operational cycle
Data Source
AI summary
A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.