Dual-Frequency PLL Switching for ZIF and LIF Transceivers

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Solution Overview

Problem

Conventional phase locked loops are unable to switch quickly enough between zero intermediate frequency (ZIF) and low intermediate frequency (LIF) modes in transceivers, which are necessary for supporting multiple communication protocols like 802.11a/b/g, due to limitations in switching local oscillator frequency during brief time windows in transceivers.

Innovation Solution

A fast switching, dual frequency phase locked loop is implemented using dual phase/frequency detectors, dual charge pumps, and a low leakage voltage controlled oscillator, allowing for separate activation and deactivation of phase/frequency detectors and tuning ports without disturbing loop filter charges, enabling rapid switching between frequencies with high accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional integer-N phase locked loop is used, then the circuit structure is simple and reliable, but the switching speed between ZIF and LIF modes is too slow to meet the requirements of multi-protocol transceivers

Engineering Contradiction:
Improveswitching speedVSAvoidphase locked loop structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The phase locked loop is segmented into two independent integer-N PLL circuits, each optimized for a specific frequency range (ZIF mode with 0-10 MHz and LIF mode with 17-27 MHz). This segmentation allows each PLL to be independently controlled and switched rapidly between modes without the complexity of a single wide-range PLL, achieving fast switching speeds while maintaining structural simplicity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The phase locked loop system is designed with multi-functionality by incorporating two independent PLL circuits that can operate in different frequency ranges. The system can universally support both ZIF and LIF modes, as well as multiple communication protocols (802.11a, 802.11b, 802.11g), by selecting the appropriate PLL circuit based on the required operating mode, thereby achieving adaptability without requiring complex reconfiguration

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the local oscillator frequency is switched rapidly between ZIF and LIF modes, then multi-protocol support is enabled, but the switching time window is extremely limited (a few microseconds)

Engineering Contradiction:
Improvemulti-protocol supportVSAvoidswitching time window
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary action by pre-configuring two independent PLL circuits with their respective frequency ranges before mode switching is required. The first PLL is pre-configured for ZIF mode (0-10 MHz) and the second for LIF mode (17-27 MHz), allowing immediate activation of the appropriate circuit when mode switching is needed, thereby reducing the actual switching time to within the available microsecond window

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A mode selection circuit acts as an intermediary between the control logic and the two PLL circuits. This intermediary rapidly selects which PLL circuit to activate based on the required operating mode (ZIF or LIF), enabling fast mode switching by eliminating the need for complex frequency synthesis reconfiguration and allowing the system to support multiple protocols within the limited time window

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If DC offset removal is performed in the digital signal processor, then fast varying DC offset can be corrected, but frequency offset between transmitter and receiver interferes with DC removal and may interfere with the first OFDM sub-carrier

Engineering Contradiction:
ImproveDC offset removal accuracyVSAvoidfrequency offset interference
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The phase locked loop serves as an intermediary that provides accurate frequency synchronization between the transmitter and receiver before DC offset removal is performed in the digital signal processor. By ensuring precise frequency alignment through the PLL's frequency synthesis and phase detection mechanisms, the frequency offset that would otherwise interfere with DC removal and contaminate the first OFDM sub-carrier is eliminated, allowing accurate DC offset correction without compromising signal integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

4Object-affected harmful factors

If ZIF mode is used in 802.11b receive mode, then adjacent channel interference is handled, but DC offset problems occur from transmitter local oscillator leakage and receiver feed through

Engineering Contradiction:
Improveadjacent channel interference rejectionVSAvoidDC offset
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The system dynamically switches between ZIF and LIF receive modes based on the communication protocol being used. For 802.11b mode, ZIF is selected to handle strong adjacent channel interference, while for 802.11a/g mode, LIF is selected to avoid DC offset problems. This dynamic adaptation allows the system to optimize performance for each protocol by selecting the appropriate operating mode, thereby managing both adjacent channel interference and DC offset issues effectively

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7630698B2Fast switching, dual frequency phase locked loop
Publication Date: 2009.12.08 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7630698B2 patent drawing
  • US7630698B2 patent drawing
  • US7630698B2 patent drawing

AI summary

A fast switching, dual frequency phase locked loop comprising dual phase/frequency detectors, dual charge pumps, a pair of loop filters, and a low leakage voltage controlled oscillator. Each phase/frequency detector and associated tuning ports of the voltage controlled oscillator can be activated and deactivated separately without disturbing the charge on the loop filters.