Dual FSB Architecture for Hot-Swap CPU Maintenance

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Solution Overview

Problem

In systems with multiple central processing units (CPUs) connected through a north bridge, a single CPU failure can lead to system downtime, and existing technologies lack efficient methods for hot-add and hot-remove operations, resulting in significant interruptions and reduced system availability.

Innovation Solution

Implementing a dual or multi Front Side Bus (FSB) architecture with electrical isolation allows for the hot-add and hot-remove of CPUs or FSBs, enabling system boot-up with a defective FSB disabled and providing component-level diagnostics for quick issue resolution, thus enhancing system availability and minimizing downtime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single CPU is connected to the north bridge, then the system structure is simple, but a single CPU failure causes total system failure and significant downtime

Engineering Contradiction:
Improvesystem availabilityVSAvoidsystem structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system is divided into multiple independent FSB segments (first FSB and second FSB), each connecting CPUs to the north bridge independently. This segmentation allows one FSB to fail while the other remains operational, preventing total system failure and enabling continued operation with reduced capacity.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If CPUs are added or removed from the system, then system configurability is improved, but system interruptions and downtime increase

Engineering Contradiction:
ImproveCPU addition and removal capabilityVSAvoidsystem downtime
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by detecting CPU presence/absence and transitioning FSB states to powered-down or powered-up states before actual CPU installation or removal. This allows hot-add and hot-remove operations to occur with minimal system interruption, as the FSB is already in the appropriate state to accommodate the CPU change.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a CPU fails, then system reliability is reduced, but the time required for identification and repair increases system downtime

Engineering Contradiction:
Improvesystem continuityVSAvoidfailure identification and repair time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements feedback mechanisms through component-level diagnostics that continuously monitor FSB and CPU health status. When a failure is detected, the system provides feedback about the specific failed component, enabling rapid identification and isolation of the problem area, which reduces the time required for repair and system restoration.

Inventive Principle:
Principle #23Feedback

4Ease of repair

If the system takes offline for CPU repair or replacement, then system availability decreases, but proper repair procedures cannot be performed

Engineering Contradiction:
ImproveCPU replacement capabilityVSAvoidsystem availability
Core Design Contradiction:
Ease of repairVSReliability

Solution Approach 1:

The system segments the FSB into independent powered-down and powered-up states, allowing CPU replacement on one FSB while the other FSB remains operational. This enables hot-swap repair operations where the system stays online and continues providing services, eliminating the need for complete system shutdowns.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7984219B2Enhanced CPU RASUM feature in ISS servers
Publication Date: 2011.07.19 HEWLETT PACKARD ENTERPRISE DEV LP
  • US7984219B2 patent drawing
  • US7984219B2 patent drawing
  • US7984219B2 patent drawing

AI summary

Generally, in accordance with embodiments of the present invention, a system having a north bridge and two or more Front Side Buses (FSBs) coupled to the north bridge is provided. The first front side bus has at least a first central processing unit coupled thereto. The second front side bus has at least a second central processing unit coupled thereto.