Dual Function Gate Structure for Flash Memory Cell Size Reduction
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Solution Overview
Problem
Current flash memory devices have large cell sizes and complex, costly fabrication processes due to the use of four separate polysilicon gates for programming and erasing operations, necessitating an improved structure for enhanced reliability and integration density.
Innovation Solution
A dual function gate structure with an upper and lower portion is introduced, acting as both an erase and control gate, reducing the number of polysilicon gates to three, including a floating gate and select gate, and allowing for minimized device size and simplified fabrication by overlapping the erase/control gate with floating gate stacks to enhance coupling ratio and operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If four separate polysilicon gates (floating gate, control gate, select gate, erase gate) are used for programming and erasing operations, then the device can perform all required functions, but the cell size becomes large and fabrication becomes complicated and costly
Solution Approach 1:
The patent combines the control gate and erase gate functions into a single dual-function gate structure. This gate has a first portion positioned adjacent to the floating gate for control functions and a second portion extending over the source region for erase functions, thereby reducing the number of separate gates from four to three while maintaining all required device functionalities
Solution Approach 2:
The dual-function gate structure is designed to perform multiple functions: the first portion acts as a control gate for programming operations, while the second portion acts as an erase gate for erasing operations. This multi-functional design reduces device complexity and cell size without sacrificing operational capabilities
2Adaptability or versatility
If four separate polysilicon gates are used, then complete programming and erasing operations can be performed, but the fabrication process becomes complicated and costly due to multiple polysilicon deposition and planarization processes
Solution Approach 1:
By merging the control gate and erase gate into a single dual-function gate structure formed from one polysilicon deposition, the patent reduces the number of fabrication steps. Instead of requiring separate polysilicon depositions and planarization processes for four gates, the invention uses a single polysilicon layer that is patterned to create both functional portions, significantly simplifying the manufacturing process
3Stability of the object's composition
If the erase gate is positioned on an opposite side of the stacked gates from the select gate, then the device structure is stable, but the device size increases
Solution Approach 1:
The dual-function gate structure transitions from a planar arrangement to a three-dimensional configuration where the gate has a first portion adjacent to the floating gate and a second portion extending over the source region. This vertical and spatial optimization allows the erase function to be integrated without increasing the lateral device footprint, effectively utilizing the third dimension to reduce overall device size while maintaining structural stability
Data Source
AI summary
A flash memory device is provided. The device comprises a substrate and a source region in the substrate. A first gate stack is positioned above the substrate and adjacent to the source region. A dual function gate structure having an upper portion and a lower portion is positioned above the source region. The upper portion of the dual function gate structure overlaps the first gate stack and the lower portion is adjacent to the first gate stack. A second gate is positioned above the substrate on an opposite side of the first gate stack from the dual function gate. A drain region is in the substrate adjacent to the second gate.