Dual Conversion Gain ADC Circuit With Selective Second Readout
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Solution Overview
Problem
Analog-to-digital converters (ADCs) in image sensors face challenges in optimizing power consumption while maintaining high resolution and signal processing efficiency, particularly in dual conversion gain operations.
Innovation Solution
The proposed solution involves an ADC circuit with a comparator and counter configuration that generates high and low conversion gain output signals based on pixel signals and ramp signals, allowing the counter to determine if a second digital signal is required, thereby controlling the generation of the second conversion gain output signal to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dual conversion gain operation is performed to improve signal processing efficiency and resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic switching between first and second conversion gain operations based on signal conditions. The counter dynamically determines whether to generate second conversion gain output signals based on the first digital signal values, enabling the system to adapt its processing depth to actual signal requirements rather than operating in a fixed dual-gain mode continuously.
Solution Approach 2:
The patent changes the conversion gain parameter dynamically based on signal conditions. By switching between first conversion gain (higher gain) and second conversion gain (lower gain) operations according to the pixel signal characteristics, the system optimizes measurement precision for different signal levels while reducing unnecessary power consumption.
2Measurement precision
If ADC processes all pixel signals through dual conversion gain to maintain high resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by selectively processing only those pixel signals that require second conversion gain through the comparator and counter. For signals that satisfy certain conditions (determined by the counter based on first digital signal values), the system performs only first conversion gain processing, avoiding unnecessary second conversion gain operations and associated power consumption.
Solution Approach 2:
The patent extracts and processes only the necessary portion of pixel signals through the full dual conversion gain path. By using the counter to identify and separate signals requiring second conversion gain from those that don't, the system removes unnecessary processing steps for signals that can be adequately handled by first conversion gain alone.
3Measurement precision
If comparator generates both first and second conversion gain output signals for all pixel signals, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces dynamic control logic where the counter determines in real-time whether the comparator should generate second conversion gain output signals. This dynamic decision-making mechanism allows the system to simplify its operation for certain signals while maintaining full capability for others, effectively managing device complexity through adaptive control rather than fixed architecture.
Data Source
AI summary
A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.