Dual Gain Imaging Digital Pixel Memory Using SRAM
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Solution Overview
Problem
Existing digital pixel Read-Out Integrated Circuits (ROICs) face limitations in simultaneous readout and integration, leading to reduced sensitivity, increased data rates, and higher power consumption due to the use of counter latches for storage and readout, which restricts dynamic range and resolution.
Innovation Solution
Implementing a system with pixels configured for Analog-to-Digital Conversion (ADC) in Rolling Integrate While Read (IWR) mode, utilizing Static Random Access Memory (SRAM) instead of traditional counter latches, allowing for both coarse and fine conversions within each pixel or group of pixels without increasing size, enabling simultaneous readout and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If counter latches are used for storage and readout in digital pixel ROICs, then data storage and readout can be achieved, but simultaneous readout and integration is prevented, reducing sensitivity and increasing required data rates
Solution Approach 1:
The patent divides the counter latch into two separate functional components: a storage latch for data retention and a readout circuit for data output. This segmentation allows the storage latch to continue integrating signal charge while the readout circuit simultaneously outputs previously stored data, resolving the contradiction between data storage/readout capability and integration time.
Solution Approach 2:
The storage latch is designed to serve dual functions: it acts as both an integration register that accumulates signal charge over time and a temporary storage element that can be read out without interrupting integration. This multi-functionality enables simultaneous readout and integration operations.
2Measurement precision
If counter latches are used for both coarse and fine conversions, then dynamic range and resolution can be improved, but pixel size and ROIC layer complexity increase significantly
Solution Approach 1:
The patent implements a dynamic readout scheme where the same storage latch is sequentially used for both coarse and fine conversions. The latch is first used to store and read out coarse conversion results, then the same latch is reused for fine conversion operations. This dynamic reuse of hardware resources achieves high dynamic range and resolution without requiring separate dedicated circuits for each conversion stage.
Solution Approach 2:
The storage latch performs multiple conversion tasks (coarse and fine) using its own internal structure without requiring additional external conversion circuits. The latch serves itself by being reconfigured and reused for different conversion stages, eliminating the need for separate conversion hardware that would increase pixel size and ROIC complexity.
3Measurement precision
If additional counter circuits are added for fine conversion, then conversion precision can be improved, but power consumption and device area increase
Solution Approach 1:
The storage latch is designed as a universal circuit element that can perform both coarse and fine conversion storage functions. By making the latch multi-functional and capable of being reused for different conversion stages, the patent eliminates the need for separate dedicated counter circuits for fine conversion, thereby reducing overall power consumption while maintaining high conversion precision.
Data Source
AI summary
Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.