2D Material Semiconductor Device With Dual Gate Stacks
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving a sub-60 mV/decade subthreshold swing, particularly due to challenges in manufacturing and scaling, especially for p-type tunneling field-effect transistors and energy-filtered FETs, which require precise control of interface defects and superlattice structures.
Innovation Solution
A semiconductor device utilizing a two-dimensional material layer with a channel region, source, and drain, along with first and second gate stacks, where the first gate stack controls carrier injection and the second gate stack manages conduction, allowing for discrete energy levels and depleted density of states to achieve a sub-60 mV/decade subthreshold swing, and is compatible with standard CMOS integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tunneling field-effect-transistor (TFET) is used to achieve sub-60 mV/decade subthreshold swing, then switching performance is improved, but manufacturing difficulty increases due to interface quality control requirements
Solution Approach 1:
The patent changes the fundamental operating mechanism from band-to-band tunneling to thermionic emission over a sharp potential barrier. This is achieved by engineering the energy band alignment at the source-channel interface using specific material combinations (e.g., MoS2 channel with WSe2 source), creating a type-II heterostructure that forms a triangular potential barrier. This parameter change in the conduction mechanism eliminates the need for heavily doped regions and complex interface engineering while achieving sub-60 mV/decade SS.
Solution Approach 2:
The patent employs composite material structures, specifically type-II heterostructures combining different two-dimensional materials (e.g., MoS2 channel with WSe2 source region). This composite approach creates favorable energy band alignment that forms a triangular potential barrier at the interface, enabling thermionic emission-based carrier injection. The composite material structure achieves both high switching performance and ease of manufacture compared to homogeneous TFET structures.
2Reliability
If energy-filtered FET with superlattice structure is used to achieve sub-60 mV/decade subthreshold swing, then switching performance is improved, but device complexity increases due to multi-layer structure requirements
Solution Approach 1:
The patent extracts and eliminates the complex superlattice structure from the device design while retaining the essential function of energy filtering. Instead of using multiple alternating semiconductor layers to create mini-bands, the invention achieves energy filtering through a single triangular potential barrier formed at the source-channel interface by type-II heterostructure engineering. This extraction of the superlattice complexity while maintaining the energy filtering function significantly simplifies the device structure.
Solution Approach 2:
Instead of using a periodic superlattice structure to create discrete energy levels, the patent inverts the approach by creating a single sharp triangular potential barrier that naturally forms discrete quantized energy levels in the well region. This inversion from periodic multi-layer structure to single-interface barrier structure achieves the same energy filtering effect with much lower device complexity.
3Productivity
If classical MOSFET scaling is continued beyond 12 nm node, then transistor density is improved, but subthreshold swing limitation prevents further performance improvement
Solution Approach 1:
The patent changes the conduction mechanism parameter from diffusion-dominated (classical MOSFET) to thermionic emission over a triangular barrier. This fundamental parameter change in the carrier injection mechanism enables subthreshold swing below 60 mV/decade, overcoming the thermal limit that constrains classical MOSFET scaling. The type-II heterostructure engineering creates the triangular potential barrier that enables this improved switching performance at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a sub-30 mV/decade subthreshold swing, reducing power consumption during state transitions, and is easily manufacturable with relaxed dimensions, suitable for both p-type and n-type configurations, and compatible with standard CMOS integration.
Implementation Method 1
each gate stack comprising a gate dielectric layer and a gate electrode, the gate dielectric layer being sandwiched between the gate electrode and the 2D material layer
Implementation Method 2
the first gate stack arranged to control the injection of carriers from the source region to the channel region
Implementation Method 3
the second gate stack arranged to control the conduction of the channel region
Data Source
AI summary
A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.