Dual-Gate 2T0C Memory Cell for Write-Current Blocking
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Solution Overview
Problem
Current three-terminal 2T0C memory cells face challenges in implementing large-scale arrays due to high routing complexity and current issues during write operations, limiting storage density improvements.
Innovation Solution
A memory circuit with a three-terminal 2T0C memory cell design using dual-gate transistors, where one transistor is used as a read transistor and another as a dual-gate transistor, with specific electrode connections and voltage control to block current paths during write operations, reducing routing complexity and enabling large-scale arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a three-terminal 2T0C memory cell is used to reduce routing complexity, then the routing complexity is reduced, but a large current occurs during write operations which prevents large-scale array implementation
Solution Approach 1:
The patent introduces a dual-gate transistor structure where the first gate serves as an intermediary control mechanism. By applying a first voltage to the first gate during write operations, the transistor channel conductivity is regulated, thereby controlling and limiting the current that flows through the bit line and memory cell, preventing the large current issue while maintaining the three-terminal simplified routing architecture
Solution Approach 2:
The patent changes the electrical parameters of the transistor by applying different voltages to the dual gate. During write operations, a specific first voltage is applied to the first gate to modulate the channel conductivity and limit current. During read operations, a different second voltage is applied to enable proper read current flow. This dynamic parameter control allows the same simplified three-terminal structure to operate correctly for both write and read operations without excessive current
2Power
If a four-terminal 2T0C memory cell is used to avoid large current during write operations, then the current issue is resolved, but the routing complexity and SA trace quantity increase making large-scale array implementation difficult
Solution Approach 1:
The patent merges the control functions of what would traditionally require separate terminals into a dual-gate transistor structure. The first gate and second gate work together to provide both current limitation during writes and proper read operation enablement, effectively combining the functions that would otherwise require separate control terminals, thus maintaining simplified three-terminal routing while controlling current
Solution Approach 2:
The dual-gate transistor serves multiple functions: the first gate provides current limitation during write operations, the second gate enables read operations, and together they allow the same bit line to be used for both writing and reading without requiring separate dedicated terminals. This multi-functionality eliminates the need for additional SA traces and complex routing while maintaining proper current control
Data Source
AI summary
A three-terminal 2T0C memory cell is formed based on a dual-gate transistor. A second transistor used as a read transistor is disposed as the dual-gate transistor. A first control electrode of the second transistor is configured to store written data during a write operation, and a second control electrode of the second transistor is configured to control a current path between a bit line and a read word line. During the write operation, a cut-off voltage may be loaded to the read word line connected to the second control electrode of the second transistor, to control the second transistor to be turned off, and the current path between the bit line and the read word line may be blocked during the write operation. In comparison with a four-terminal 2T0C memory cell, complexity and an area of SA routing are reduced, and storage density can be effectively improved.