Dual-Gate Adiabatic Logic Cell for Dynamic Threshold Control
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Solution Overview
Problem
Adiabatic logic cells face limitations in reducing energy consumption due to residual non-adiabatic energy dissipation and increased leakage currents when attempting to lower threshold voltages, which affects both dynamic and static energy consumption.
Innovation Solution
An adiabatic logic cell design incorporating a dual-gate MOS transistor with a front gate and a back gate, where the periodic variable bias voltage is synchronized with the supply voltage, varying in phase or phase opposition to modulate the threshold voltage and reduce energy dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage VDD is reduced to decrease dynamic consumption, then energy consumption is improved, but the threshold voltages of transistors decrease causing increased leakage currents and higher static consumption
Solution Approach 1:
The patent applies dynamics by making the transistor threshold voltage time-dependent through a periodic bias voltage applied to the back gate. The threshold voltage varies periodically in sync with the supply voltage, being low during charging phases (reducing dynamic consumption) and high during idle phases (reducing static consumption from leakage currents). This dynamic adjustment resolves the contradiction between dynamic and static energy consumption.
Solution Approach 2:
The patent changes the threshold voltage parameter of the transistor dynamically by applying a periodic bias voltage to the back gate of the dual-gate transistor. This parameter change allows the threshold voltage to adapt to different operational phases: low threshold during active charging to minimize dynamic energy loss, and high threshold during idle periods to minimize leakage currents, thereby resolving the energy consumption contradiction.
2Loss of energy
If the threshold voltage of transistors is reduced to decrease non-adiabatic energy dissipation, then energy loss is improved, but leakage currents increase causing higher static consumption
Solution Approach 1:
The patent implements periodic action by applying a periodic bias voltage to the back gate of the dual-gate transistor, causing the threshold voltage to oscillate periodically. During active phases, the threshold voltage is reduced to minimize non-adiabatic energy dissipation during charging/discharging. During idle phases, the threshold voltage is increased to reduce leakage currents. This periodic modulation resolves the contradiction between reducing energy loss and minimizing static consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes non-adiabatic energy loss and reduces static consumption by dynamically controlling the threshold voltage, achieving efficient energy management in adiabatic logic cells.
Implementation Method 1
The present disclosure relates to the field of integrated circuits comprising cells implementing logic functions... realised based on field-effect transistors, for example using CMOS technology
Implementation Method 2
In adiabatic logic, rather than abruptly charging and discharging the output capacitances CL of the cells each time their state changes, which is the case in classic logic, an effort is made to effect the charging and discharging of the capacitances CL in a gradual manner
Data Source
AI summary
An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.