Dual-Gate a-IGZO TFT Preventing Threshold Voltage Drift
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Solution Overview
Problem
The threshold voltage of a-IGZO thin film transistors (TFTs) easily drifts under negative bias illumination stress (NBIS), making it difficult to achieve large-scale production in liquid crystal display (LCD) panels.
Innovation Solution
A thin film transistor array substrate is designed with a bottom gate, a semiconductor oxide layer of amorphous indium gallium zinc oxide, an etch blocking layer, and a top gate structure, where the top gate contacts the bottom gate through a via, and the pixel electrode is made of indium tin oxide, to prevent threshold voltage drift during NBIS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a-IGZO thin film transistors are used in LCD panels, then electron mobility and on/off ratio are improved, but threshold voltage stability deteriorates under negative bias illumination stress
Solution Approach 1:
The transistor gate is divided into two separate gates: a bottom gate and a top gate. This segmentation allows independent control and optimization of different transistor characteristics. The bottom gate provides the primary switching function with high electron mobility, while the top gate compensates for threshold voltage drift under NBIS conditions, thus resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent employs a composite structure combining a-IGZO semiconductor layer with dual gate electrodes. The combination of bottom gate (providing high mobility) and top gate (providing stability) creates a composite device that achieves both high electron mobility and threshold voltage stability under NBIS, overcoming the limitations of single-gate a-IGZO transistors.
2Reliability
If conventional a-Si thin film transistors are used, then threshold voltage stability is maintained, but electron mobility and on/off ratio are limited
Solution Approach 1:
The patent changes the material parameter from conventional a-Si to a-IGZO semiconductor, which inherently provides higher electron mobility and better on/off ratio. The dual gate structure then compensates for the NBIS-induced threshold voltage drift, allowing the device to achieve both high mobility and stability that neither material alone could provide.
3Device complexity
If a-IGZO TFTs are used without dual gate structure, then device complexity is reduced, but large-scale production feasibility deteriorates due to threshold voltage drift
Solution Approach 1:
By segmenting the gate into bottom and top gates, the patent enables precise control over transistor characteristics. This segmentation allows the device to maintain stable threshold voltage during NBIS, which is critical for large-scale production where consistent performance across millions of pixels is required, thus improving productivity despite increased structural complexity.
Data Source
AI summary
A thin film transistor array substrate includes a bottom gate disposed on a substrate and a bottom gate insulating layer covering the bottom gate, a semiconductor oxide layer disposed on the bottom gate insulating layer and an etch blocking layer covering the semiconductor oxide layer and including a first via, a drain disposed on the etch blocking layer and contacting with the semiconductor oxide layer through the first via and an insulating protection layer covering the drain, a second via arranged in the insulating protection layer, the etch blocking layer and the bottom gate insulating layer, a top gate disposed on insulating protection layer and contacting with the bottom gate through the second via. A method for manufacturing the thin film transistor array substrate is also disclosed. The thin film transistor prevents the threshold voltage thereof from being drifted in a case of negative bias illumination stress (NBIS).