Dual-Gate Array Substrate With Alternating Lines for Higher Transmission
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Solution Overview
Problem
The increase in display panel resolution leads to higher performance and cost for drive integrated circuits (ICs), necessitating a dual-gate drive design to reduce costs while improving yield, but this design faces challenges in opening ratio and transmission.
Innovation Solution
A dual-gate array substrate design with alternately arranged primary and secondary signal lines, where the secondary signal lines are connected to common electrodes, and main electrodes are configured to cover primary signal lines without overlapping pixel electrodes, reducing coupling capacitance and increasing opening ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dual-gate drive design is used to reduce cost and improve yield, then manufacturing cost and binding yield are improved, but opening ratio and transmission are worsened
Solution Approach 1:
The signal line is segmented into primary signal lines and secondary signal lines arranged alternately. Primary signal lines are connected to pixel units while secondary signal lines are connected to common electrodes. This segmentation allows the dual-gate drive structure to maintain cost and yield benefits while improving opening ratio by strategically positioning signal lines to minimize blocking of light paths.
Solution Approach 2:
Different regions of the array substrate are assigned different signal line configurations. Primary signal lines are positioned in regions requiring high driving capability, while secondary signal lines are positioned to optimize light transmission. This local differentiation allows the dual-gate drive design to achieve both manufacturing efficiency and improved optical performance.
2Reliability
If main electrodes are enlarged to cover primary signal lines, then coupling capacitance is reduced, but opening ratio is worsened
Solution Approach 1:
Secondary signal lines serve as intermediaries between pixel units and common electrodes. By introducing these intermediate signal lines, the design can stabilize coupling capacitance through proper signal line configuration without requiring excessive enlargement of main electrodes, thus preserving opening ratio while maintaining electrical performance.
Solution Approach 2:
The solution moves from a single-dimensional electrode expansion approach to a two-dimensional signal line arrangement. By alternately positioning primary and secondary signal lines across the substrate, the design achieves capacitance stabilization through spatial distribution rather than simple electrode area increase, thereby maintaining optical transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances transmission and opening ratio by stabilizing voltage and avoiding coupling capacitance, thus improving display performance and reducing the need for larger electrodes.
Implementation Method 1
main electrodes covering primary signal lines to reduce coupling capacitance
Implementation Method 2
secondary signal lines connected to common electrodes to prevent unwanted capacitance, allowing for a stable voltage application
Data Source
AI summary
A dual-gate array substrate includes: a plurality of gate lines arranged in a first direction and each extended in a second direction that is perpendicular to the first direction; a plurality of primary signal lines and secondary signal lines arranged alternately in the second direction and extended in the first direction; and a plurality of pixel units. The primary signal lines are connected to a drive unit, and connected respectively to the pixel units that are adjacent thereto. Common electrodes include a plurality of main electrodes and a plurality of branching electrodes. An orthographic projection of the main electrode on the dual-gate array substrate does not overlap with those of corresponding ones, adjacent to the main electrode, of the pixel electrodes and at least covers the primary signal line. Each gate line includes a protrusion protruded in the first direction.