Dual Gate Line Access Transistors for Folded BEOL DRAM Arrays
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling down devices and embedding dynamic random access memory (DRAM) in advanced nodes, particularly due to area penalties and design-rule-violations when implementing folded bit line architectures in standard logic processes.
Innovation Solution
The implementation of back-end-of-line (BEOL) embedded dynamic random access memory (DRAM) using thin film transistors (TFTs) in a folded bit line configuration, which includes a two-dimensional array of unit cell structures with semiconducting metal oxide active layers, allowing for improved noise immunity and signal-to-noise ratio without area penalties, and is compatible with CMOS-under-Array (CuA) configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If folded bit line architecture is implemented in standard logic processes, then area efficiency is improved, but design rule violations occur
Solution Approach 1:
The patent transitions from planar 2D transistor structures to 3D vertically-stacked transistor structures. Multiple transistor layers are stacked vertically above each other, utilizing the third dimension (height) to increase device density without expanding the lateral footprint. This vertical stacking enables folded bit line architecture to achieve area efficiency while maintaining compliance with manufacturing design rules by reducing lateral feature size constraints.
2Productivity
If devices are scaled down to advance nodes, then integration density is improved, but manufacturing precision requirements become more stringent
Solution Approach 1:
By stacking transistor layers vertically, the patent achieves higher integration density without further lateral scaling. The vertical dimension provides additional space for multiple device layers while maintaining larger lateral dimensions that are easier to manufacture with current precision capabilities. This approach decouples integration density from lateral feature size, allowing density improvement through vertical stacking rather than continued miniaturization.
Solution Approach 2:
The patent divides the transistor structure into multiple discrete layers stacked vertically, with each layer containing specific components (e.g., source/drain regions, channels, gates). This segmentation allows independent optimization and manufacturing of each layer, reducing the cumulative precision requirements compared to monolithic scaled-down structures. Each layer can be fabricated and assembled separately, then stacked to form the complete device.
3Area of stationary object
If BEOL embedded DRAM is implemented, then FEOL device area is minimized, but noise immunity challenges arise
Solution Approach 1:
The patent places DRAM transistor layers vertically above FEOL logic devices in the back-end-of-line (BEOL) process stages. This vertical stacking in higher process layers allows DRAM to be embedded without occupying lateral FEOL area, while the physical separation in vertical space and use of BEOL-compatible materials helps reduce noise coupling between DRAM and FEOL devices.
Data Source
AI summary
A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.