Dual Gate CMOS Fabrication with Selective Native Oxide Removal
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Solution Overview
Problem
The leading edge Si CMOS industry faces challenges in scaling down gate stacks and achieving high-quality gate stacks for sub-10 nm geometry devices, particularly when co-integrating SixGe1-x p-FETs with group III-V compound n-FETs, which require different interface materials between the channel materials and the gate stack.
Innovation Solution
A method is developed to fabricate dual gate stacks for CMOS structures by forming native oxide layers on semiconductor substrates with SixGe1-x and group III-V materials, followed by selective cleaning to remove the native oxide layer from the III-V material surfaces, allowing for the deposition of high-k dielectric and metal gate layers without native oxides, enabling efficient co-fabrication of p-FET and n-FET transistors on a common substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If native oxide layers are formed on both SixGe1-x and group III-V channel structures, then interface control is improved for SixGe1-x, but interface quality deteriorates for group III-V due to presence of native oxides
Solution Approach 1:
The patent applies local quality by treating the two channel structures differently: SixGe1-x retains its native oxide layer for interface control, while group III-V has its native oxide layer selectively removed. This differential treatment optimizes the interface characteristics for each material type according to its specific requirements.
Solution Approach 2:
The patent extracts the harmful element (native oxide layer) selectively from the group III-V channel structure surface while preserving it on the SixGe1-x surface. The selective cleaning process removes only the group III-V native oxide, leaving the SixGe1-x native oxide intact to serve as an interface control layer.
2Reliability
If different interface materials are used for SixGe1-x and group III-V, then device performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct steps for different channel structures. The selective cleaning process creates different interface conditions for SixGe1-x and group III-V materials, allowing each to have optimized interface characteristics appropriate to its material properties.
Solution Approach 2:
The native oxide layer serves as an intermediary element with different roles for different materials: on SixGe1-x it acts as a beneficial interface control layer, while on group III-V it is treated as a harmful contaminant to be removed. This intermediary approach allows single process steps to achieve differentiated results.
3Productivity
If gate stack is scaled down for sub-10 nm devices, then device density increases, but gate stack quality and control become more difficult
Solution Approach 1:
The patent performs preliminary action by forming and selectively treating native oxide layers on the channel structures before gate stack formation. This pre-preparation of optimized interfaces ensures that when the gate stack is subsequently formed at scaled dimensions, the underlying interface quality supports reliable device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the scalable and efficient co-fabrication of dual gate CMOS structures with improved interface control, reducing defects and enabling the formation of high-quality gate stacks for both SixGe1-x and III-V channel materials, thereby overcoming the limitations of existing technologies in achieving sub-10 nm geometry devices.
Implementation Method 1
oxidizing a surface of the first channel structure and a surface of the second channel structure, thereby forming a first native oxide layer comprising an oxide of the first semiconductor material and a second native oxide layer comprising an oxide of the second semiconductor material
Implementation Method 2
The first native oxide layer and the second native oxide layer are treated by a selective cleaning process that selectively removes the second native oxide layer only
Data Source
AI summary
A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.