Dual Gate Cut Structure for Backside Power Cell Height Scaling
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Solution Overview
Problem
Existing semiconductor devices face challenges in cell height scaling due to merging of epitaxial semiconductor material and limitations imposed by anisotropically etched gate cut structures, which consume significant gate electrode surface area and hinder device integration.
Innovation Solution
Employing a shallow front gate cut combined with a back gate cut that extends from the backside to section the gate structure, along with backside source/drain cuts to prevent merging and minimize the width of the gate cut, allowing for improved cell height scaling and device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the depth of gate cut is increased to section the gate structure, then the gate structure is effectively divided, but the upper width of the gate cut increases consuming significant gate electrode surface area
Solution Approach 1:
The gate cut structure is divided into two separate cuts: a front gate cut from the front surface and a back gate cut from the back surface. This segmentation allows each cut to be shallower, reducing the upper width and preserving gate electrode surface area while still achieving complete sectioning of the gate structure.
Solution Approach 2:
The solution transitions from a single-dimensional (front-only) gate cut to a two-dimensional approach by introducing a back gate cut. This adds a new dimension (back surface access) to the gate cutting process, enabling the structure to be sectioned with shallower individual cuts that preserve more gate electrode surface area.
2Productivity
If cell height is scaled down to increase device integration, then device density improves, but epitaxial semiconductor material merges limiting further scaling
Solution Approach 1:
The separation of gate cutting operations into front and back components creates distinct isolation regions that prevent merging of epitaxial semiconductor material during scaling. This segmentation maintains material separation even as cell height is reduced to increase device integration.
3Productivity
If cell height is scaled down, then device density increases, but the width of gate cut consumes a greater proportion of gate electrode
Solution Approach 1:
By accessing the gate structure from both front and back surfaces, the solution distributes the cutting burden across two dimensions. This allows shallower individual cuts with reduced upper widths, preserving gate electrode contact surface area even as cell height is scaled down to increase device density.
Data Source
AI summary
A semiconductor device includes a row of source/drain regions delineating a frontside and a backside opposite the frontside of the semiconductor device. A front gate cut from the frontside of the device has a depth that is less than a height of a gate structure for the semiconductor device. A back gate cut from the backside of the semiconductor device contacts the front gate cut.