Dual-Gate Display Panel Data Line Reduction
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Solution Overview
Problem
Current display panels face challenges in reducing the number of data lines while minimizing afterimages and ensuring sufficient charging time, especially for high-frequency gaming monitors, as existing technologies either increase panel cost or compromise display quality.
Innovation Solution
A dual-gate structure display panel design is implemented, featuring a common electrode, multiple gate lines, and specific switching elements, which reduces data lines by half, allows for efficient image signal and black signal writing, and secures charging time by optimizing gate driver configuration and signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a dual-gate structure is implemented to reduce the number of data lines, then the number of data lines is reduced to 1/2, but the writing time to each pixel becomes about 1/2 of that in the normal structure
Solution Approach 1:
The gate lines are divided into two sets (first gate lines and second gate lines) that operate independently. Each set controls different pixel rows, allowing parallel writing operations. This segmentation enables the system to maintain reduced data line count while compensating for the shortened writing time through parallel processing.
Solution Approach 2:
The patent implements dynamic control of the dual-gate structure by selectively activating first gate lines for odd pixel rows and second gate lines for even pixel rows. This dynamic switching allows flexible adjustment of writing timing and enables parallel operation modes that compensate for the reduced writing time per pixel while maintaining the reduced data line configuration.
2Object-affected harmful factors
If the panel frequency is doubled to suppress afterimages, then the afterimage is improved, but the writing time to each pixel becomes about 1/2 of that in the normal structure
Solution Approach 1:
By segmenting the gate control into two independent sets that can operate in parallel, the system can handle the doubled panel frequency required for afterimage suppression. The parallel operation of first and second gate lines ensures that sufficient writing time is allocated to each pixel even at the higher frequency, while still achieving the afterimage suppression benefit.
Solution Approach 2:
The patent ensures continuous and efficient use of writing time by implementing a scanning mechanism that systematically addresses all pixel rows using the dual-gate structure. This continuous operation mode maximizes the utilization of available writing time at doubled panel frequency, ensuring that image signals are written completely while maintaining high refresh rates for afterimage suppression.
3Object-affected harmful factors
If both the number of data lines is reduced and the panel frequency is doubled, then the number of data lines is reduced to 1/2 and afterimage is suppressed, but the writing time to each pixel becomes about 1/4 of that in the normal structure
Solution Approach 1:
The dual-gate structure segments the pixel rows into two groups controlled by different gate line sets, enabling parallel writing operations. This segmentation allows the system to simultaneously achieve reduced data line count and doubled panel frequency while maintaining adequate writing time through coordinated parallel processing of the two pixel row groups.
Solution Approach 2:
The patent implements dynamic scanning control that alternates between first and second gate lines to address different pixel rows. This dynamic time-division multiplexing approach ensures that each pixel receives sufficient writing time despite the overall doubled panel frequency and reduced data line count, by optimizing the timing and sequence of signal writing across the dual-gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the number of data lines, suppresses afterimages, and secures sufficient charging time for each pixel, enhancing display quality and reducing panel costs, particularly suitable for high-frequency gaming monitors.
Implementation Method 1
a voltage is applied to the liquid crystal composition to change the alignment of liquid crystal molecules, thereby controlling the amount of light transmitted through the liquid crystal panel
Implementation Method 2
a common electrode configured to generate an electrical field between the common electrode and each of the plurality of pixel electrodes
Data Source
AI summary
A display panel including: a plurality of pixels arranged in a longitudinal direction and a lateral direction; a plurality of pixel electrodes; a common electrode; a first, second, third, and fourth gate lines extending in the lateral direction; and a first and second data lines, and a common line extending in the longitudinal direction, in which the plurality of pixels include a first pixel having a first pixel electrode and a second pixel adjacent to the first pixel in the lateral direction and having a second pixel electrode, the third gate line is arranged to overlap the first and the second pixel electrodes, the common line is arranged between the first and the second pixel electrodes, and the display panel further includes a first switching element connected to the first pixel electrode, the common line, and the third gate line, and a second switching element connected to the second pixel electrode, the common line, and the third gate line.