Dual-Gate Display TFT Structure for High-Resolution Scan Timing
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Solution Overview
Problem
High-resolution display devices face challenges in securing a sufficient scan delay margin, leading to risks of improper horizontal synchronization and driving signal issues due to shortened scan on-time.
Innovation Solution
The display device incorporates a dual-layer gate insulating structure with different dielectric constants and thicknesses, allowing for operation in multiple driving modes based on gate signal frequencies to manage scan delay and improve signal reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high resolution is implemented, then display quality is improved, but scan delay margin becomes insufficient
Solution Approach 1:
The patent implements a dual-gate structure where the first gate controls the main current flow and the second gate dynamically adjusts the channel conductivity. This dynamic control mechanism allows the transistor to adapt to high-resolution display requirements while maintaining sufficient scan delay margin through real-time conductivity modulation in the active layer.
Solution Approach 2:
The patent changes the physical parameters of the transistor by introducing a second gate that independently controls the channel properties. By adjusting the voltage applied to the second gate, the conductivity of the active layer can be modulated, enabling the system to maintain reliable scan delay margins while operating at high resolution by dynamically altering the electrical parameters of the transistor channel.
2Measurement precision
If scan on-time is shortened, then high resolution is achieved, but driving signal reliability deteriorates
Solution Approach 1:
The dual-gate transistor structure enables dynamic control of the channel conductivity through the second gate. This allows the transistor to maintain reliable driving signal characteristics even when scan on-time is shortened for high-resolution displays, as the second gate can rapidly adjust the channel properties to ensure proper signal transmission within the reduced time window.
Solution Approach 2:
The second gate can be used to pre-condition the channel before the actual scan signal arrives. By adjusting the second gate voltage in advance, the transistor channel is prepared to quickly and reliably respond to the incoming driving signal, ensuring signal integrity even when the overall scan on-time is shortened for high-resolution operation.
3Reliability
If dual gate structure is added, then scan delay margin is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of two gates into a single transistor structure, where the first gate and second gate work together to control the same active layer. This combined approach allows the dual-gate transistor to achieve improved scan delay margin while sharing common structural elements (such as the active layer and source-drain contacts), thereby reducing the overall complexity compared to implementing two separate transistor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of driving signals and improves display quality by securing scan on-time and reducing the risk of afterimages and color deviations in high-resolution displays.
Implementation Method 1
The first gate insulating layer may have a first dielectric constant, and the second gate insulating layer may have a second dielectric constant. The first dielectric constant and the second dielectric constant may be different from each other.
Data Source
AI summary
A display device includes a first layer disposed on a base layer and including a first gate electrode, a first gate insulating layer, and an active layer, and a second layer disposed on the first layer and including a second gate electrode, a second gate insulating layer, and the active layer. The first layer and the second layer share the active layer. The first gate insulating layer has a first dielectric constant, and the second gate insulating layer has a second dielectric constant. The first dielectric constant and the second dielectric constant are different from each other.