Dual-Gate Display Panel Transistor for Precise Channel Control
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Solution Overview
Problem
The size of transistors in display panels cannot meet preset requirements due to manufacturing processes, affecting the performance and functionality of the display panel.
Innovation Solution
A display panel design with a specific transistor structure and manufacturing method, including a first transistor with a unique active layer and conductive layer configuration, utilizing oxide semiconductors and precise etching techniques to achieve desired sheet resistances and channel regions, and a conducting treatment using a mask to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional transistor structure is used, then manufacturing process is simple, but transistor size cannot meet preset requirements
Solution Approach 1:
The active layer is divided into multiple segments (first active part, second active part, third active part) with different functions. The first active part forms source/drain regions, the second active part forms channel regions, and the third active part forms additional channel regions. This segmentation allows precise control of transistor dimensions and enables meeting preset size requirements while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces a vertical stacking structure with multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) and gate structures arranged in different dimensions. The first gate is formed by the first conductive layer, the second gate by the second conductive layer, creating a multi-dimensional gate control structure that enables precise transistor size control without complicating the manufacturing process excessively.
2Reliability
If conventional transistor structure is used, then device complexity is low, but transistor performance (sheet resistance) is insufficient
Solution Approach 1:
Different regions of the active layer are assigned different materials or properties to achieve local optimization. The first active part, second active part, and third active part can have different sheet resistances tailored to their specific functions. This local quality differentiation improves overall transistor performance while the structured approach keeps device complexity manageable.
Solution Approach 2:
The patent employs composite material structures in the conductive layers and active layers, combining different materials with complementary properties. The first conductive layer, second conductive layer, and third conductive layer use composite material configurations that optimize electrical conductivity and sheet resistance characteristics, thereby enhancing transistor performance without excessive complexity.
3Manufacturing precision
If precise etching techniques are used, then channel region control is improved, but manufacturing process complexity increases
Solution Approach 1:
Mask patterns are formed in advance before etching to define the precise channel region boundaries. The mask layers are prepared beforehand with the correct geometry, allowing the etching process to proceed with high precision without requiring complex real-time adjustments. This preliminary action simplifies the overall manufacturing process while achieving precise channel region control.
Solution Approach 2:
Mask layers and barrier layers serve as intermediaries between the etching process and the final channel region structure. These intermediary layers facilitate precise pattern transfer during etching, enabling accurate channel region definition while the mask formation process remains a standard, manageable manufacturing step.
Data Source
AI summary
A display panel includes base substrate, second conductive layer, second active layer, third gate insulating layer, third conductive layer in sequence. The second conductive layer includes first conductive part forming first gate of first transistor. The second active layer includes first active part including first and second sub-active parts and third sub-active part therebetween. The first and second sub-active parts form first and second electrodes of first transistor, and portion of the third sub-active part forms channel region of first transistor. Orthographic projection of the first conductive part on the base substrate covers that of the third sub-active part. Orthographic projection of the third gate insulating layer on the base substrate covers that of the first active part. The third conductive layer includes second conductive part forming second gate of first transistor. Orthographic projection of the second conductive part on the base substrate covers that of the channel region.