Dual-Gate DRAM Cell for GIDL Reduction
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges in maintaining data retention due to finite data retention characteristics, leading to the need for frequent refresh operations. Additionally, gate-induced drain leakage (GIDL) current in DRAM memory cells contributes to data loss and degrades refresh characteristics.
Innovation Solution
The proposed memory device incorporates a memory cell array with dual-gate cell transistors and capacitors. A sub-word line driver block and a row decoder are used to generate and control word line signals and enable signals, which are applied to the dual gates of the memory cells. This configuration reduces GIDL current by controlling the voltage levels of the word line enable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM performs frequent refresh operations to maintain data stored in cell capacitors, then data retention is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the word line control into two separate gates: a first gate receiving a first word line signal and a second gate receiving a second word line signal. This segmentation allows independent control of the memory cell transistor, enabling reduced refresh operations while maintaining data retention by precisely controlling when and how the cell is accessed and refreshed.
2Reliability
If DRAM performs frequent refresh operations to maintain data, then data retention is improved, but power consumption increases
Solution Approach 1:
By segmenting the gate control into two independent gates with separate signal lines, the patent enables selective activation of refresh operations. The dual gate structure allows the memory cell to be accessed or refreshed only when necessary, reducing unnecessary power consumption associated with frequent global refresh operations.
Solution Approach 2:
The patent applies different voltage levels and signal characteristics to different gates locally. The first gate receives a first word line signal with specific voltage characteristics, while the second gate receives a second word line signal with different characteristics. This local differentiation enables precise control of the memory cell state, allowing data retention without requiring full-strength frequent refreshes across the entire array.
3Reliability
If GIDL current is reduced by controlling voltage levels of word line enable signals, then data loss is reduced, but device complexity increases
Solution Approach 1:
The patent segments the word line enable signal into two separate signal lines (first word line signal and second word line signal) that can be independently controlled. This segmentation allows precise voltage level management at each gate, reducing GIDL current by ensuring proper voltage relationships between gates without requiring complex multi-signal coordination circuits.
Solution Approach 2:
The patent changes the voltage parameters of the word line signals applied to different gates. By controlling the voltage levels, timing, and polarity of the first and second word line signals independently, the patent reduces the electric field stress that causes GIDL current while maintaining proper memory cell operation. This parameter control is achieved through the dual gate structure rather than complex signal processing.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cells, a sub word line driver block including a plurality of sub word line drivers configured to output word line signals, which are respectively provided to the plurality of memory cells, and a row decoder configured to generate word line enable signals, which are respectively provided to the plurality of memory cells. Each of the memory cells includes a cell transistor including dual gates, and a capacitor connected to the cell transistor. A word line enable signal applied by the row decoder is connected to one of the dual gates.