Two-Transistor DRAM Cell With Dual-Gate Read Current Blocking
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Solution Overview
Problem
Existing 2T DRAM cells face issues with undesired current flow during read operations, leading to errors and complications in refresh operations due to the need for multiple voltage applications and unselected cell interference.
Innovation Solution
A 2T DRAM cell design with a dual-gate read transistor, where the off gate is connected to a source line, blocking unselected cell operations and simplifying the refresh process by reducing the number of signal lines to three, including a write word line, bit line, and source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 2T0C DRAM cell structure is used, then the device achieves high integration density and low leakage current, but undesired current flow occurs during read operations causing errors and complex refresh operations
Solution Approach 1:
The read transistor gate is segmented into two independent gates: a first gate connected to the storage node and a second gate connected to the source line. This segmentation allows independent control of the transistor's on/off state, enabling the device to block undesired current flow from unselected cells while maintaining proper read operation functionality.
2Ease of operation
If multiple voltage applications are used for read operations, then the read operation can be performed, but the refresh operation becomes complicated and error-prone
Solution Approach 1:
The dual-gate read transistor structure enables the cell to self-block undesired current flow during read operations without requiring complex external control circuits or multiple voltage applications. The transistor automatically prevents leakage current from unselected cells, simplifying the refresh operation to a single voltage application while maintaining reliable read functionality.
3Device complexity
If the number of signal lines is reduced to three, then the device complexity is reduced, but the ability to perform read operations without unselected cell interference is compromised
Solution Approach 1:
The first gate and second gate are merged into a single read transistor structure with integrated control. This merging allows the transistor to simultaneously respond to both the storage node voltage and source line voltage, enabling reliable read operations with only three signal lines (write word line, bit line, and source line) while preventing unselected cell interference through the coordinated action of the two gates.
Data Source
AI summary
Disclosed is a two-transistor (2T) DRAM cell, including a write transistor configured to transmit information of a bit line connected to one terminal of the write transistor to a storage node which is the other terminal of the write transistor in response to a signal of a write word line during a write operation, and a read transistor including a main gate that is activated in response to a voltage of the storage node and an off gate that is formed at a place that comes into contact with the main gate and that is activated in response to a voltage of a source line and configured to transmit a voltage corresponding to the voltage of the storage node to the bit line during a read operation.