Dual Gate Driver Circuit for Low-Delay Active-Matrix Displays
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Solution Overview
Problem
Display devices driven by an active matrix mode face issues with signal delay and distortion due to parasitic capacitance and resistance in gate lines, particularly as the pixel portion increases in quality, affecting the performance of gate drivers and image display.
Innovation Solution
The implementation of a display device with a first and second gate driver, each including flip flop circuits and transfer signal generation circuits, where the output of one circuit is connected to the input of the next with a half clock cycle delay, reducing signal delay and distortion by optimizing the electrical connections and circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel portion is increased in quality, then the display quality is improved, but the signal delay and distortion due to parasitic capacitance and resistance in gate lines increases
Solution Approach 1:
The gate driver is divided into multiple gate drivers (first gate driver and second gate driver) that are provided at different locations. Each gate driver controls a specific region of the pixel portion, which segments the overall gate driving function. This segmentation reduces the distance that control signals must travel through gate lines, thereby reducing the impact of parasitic capacitance and resistance while maintaining high display quality.
2Device complexity
If a single gate driver is provided close to one side of the pixel portion, then the device complexity is reduced, but the display portion becomes asymmetric and signal transmission issues arise
Solution Approach 1:
Instead of using one complex gate driver at one location, the gate driving function is segmented into multiple simpler gate drivers positioned at different locations. This segmentation achieves symmetry in the display portion while keeping each individual gate driver relatively simple in structure.
3Reliability
If multiple gate drivers are provided to reduce signal delay, then the signal transmission is improved, but the device complexity increases
Solution Approach 1:
The gate driver system is segmented into multiple independent gate drivers, each responsible for a specific region. This segmentation improves signal transmission by reducing line lengths while the modular nature of each gate driver keeps the overall device complexity manageable through functional distribution.
Data Source
AI summary
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.