Dual Gate Driver Layout for Low-Distortion Display Signals
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Solution Overview
Problem
Display devices driven by an active matrix mode face issues with signal delay and distortion due to parasitic capacitance and resistance in gate lines, particularly as the pixel portion increases in quality, affecting image display.
Innovation Solution
The implementation of a display device with a first and second gate driver, each connected to odd-numbered and even-numbered gate lines respectively, utilizing flip flop circuits and transfer signal generation circuits to output signals with a half clock cycle delay, reducing signal delay and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate driver is provided close to one side of the pixel portion, then the device complexity is reduced, but the display portion becomes unevenly positioned and signal delay increases
Solution Approach 1:
The gate driver is divided into two separate gate drivers (first gate driver and second gate driver) positioned at opposite sides of the pixel portion. Each gate driver controls alternate gate lines (odd-numbered and even-numbered respectively), distributing the control function across multiple components to reduce signal delay while maintaining manageable complexity
Solution Approach 2:
The gate drivers are positioned in different spatial locations (left side and right side of the pixel portion) rather than concentrating them in one location. This spatial distribution balances the display portion positioning and reduces signal travel distance, addressing the time loss issue
2Manufacturing precision
If the pixel portion quality is increased, then the display quality is improved, but parasitic capacitance and resistance effects become more significant causing signal distortion
Solution Approach 1:
By segmenting the gate driver into two separate units positioned at opposite sides, each gate driver serves a smaller region of the pixel portion. This reduces the length of gate lines and consequently minimizes the parasitic capacitance and resistance effects that increase with line length, allowing higher pixel quality without signal distortion
3Loss of time
If gate drivers are divided and placed in both right side and left side of the pixel portion, then signal delay is reduced, but the device complexity increases
Solution Approach 1:
Both gate drivers use identical circuit configurations and control mechanisms, with each driver universally handling its assigned gate lines (odd or even) in the same manner. This standardized approach reduces design complexity despite having multiple drivers, as the same proven circuit design is replicated rather than creating new complex circuits
Solution Approach 2:
The gate lines are segmented into two separate groups (odd-numbered and even-numbered), with each group controlled by a dedicated gate driver. This functional segmentation allows parallel operation and reduces signal delay while maintaining manageable complexity through clear division of control responsibilities
Data Source
AI summary
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.