Dual Gate Driver Circuit for Low-Distortion Display Scanning
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Solution Overview
Problem
In display devices driven by an active matrix mode, the presence of parasitic capacitance and resistance in gate lines leads to signal delays and distortions, particularly as the pixel portion becomes more high-quality, affecting the display's ability to accurately show images.
Innovation Solution
The implementation of a display device with a first and second gate driver, each connected to odd-numbered and even-numbered gate lines respectively, utilizing flip-flop circuits and transfer signal generation circuits to input signals with a half clock cycle delay, reducing signal delay and distortion by direct connection of output terminals to input terminals of subsequent circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel portion is made high-quality with extended gate lines, then the display quality is improved, but signal delay and distortion increase due to parasitic capacitance and resistance
Solution Approach 1:
The gate driver is divided into multiple segments (first gate driver and second gate driver) that control different sets of gate lines. Each segment processes signals independently, reducing the cumulative effect of parasitic capacitance and resistance in long gate lines. This segmentation allows high-quality display with extended pixel portions while maintaining signal integrity.
2Device complexity
If a single gate driver is used, then the device complexity is reduced, but the display portion becomes asymmetric and signal distortion increases
Solution Approach 1:
The gate driver functionality is segmented into two separate gate drivers positioned at opposite sides of the pixel portion. This segmentation achieves symmetric display geometry while distributing the signal driving task, preventing signal distortion that would occur with a single asymmetric gate driver configuration.
3Length of stationary object
If gate drivers are placed close to the pixel portion, then the connection length is reduced, but the display becomes asymmetric
Solution Approach 1:
The gate driver function is segmented and distributed to two separate locations (first and second gate drivers at opposite sides). This segmentation allows each driver to be positioned close to its controlled pixel region, minimizing gate line lengths while maintaining overall display symmetry through balanced configuration.
4Area of stationary object
If shift registers are connected through gate lines, then the circuit area is reduced, but signal delay and distortion increase
Solution Approach 1:
Transfer signal generation circuits are introduced as intermediary components between the shift registers and gate lines. These intermediaries generate optimized transfer signals that compensate for parasitic effects, enabling reliable signal transmission while maintaining compact circuit area through efficient signal routing.
Data Source
AI summary
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.