Dual Gate Driver Layout for Low-Distortion Display Signals
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Solution Overview
Problem
Display devices driven by an active matrix mode face issues with signal delay and distortion due to parasitic capacitance and resistance in gate lines, especially as pixel quality increases.
Innovation Solution
The implementation of a display device with a gate driver formed using unipolar transistors, featuring a structure with a first and second gate driver connected to odd and even-numbered gate lines respectively, and including flip flop circuits and transfer signal generation circuits to manage signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel portion is made high-quality with increased definition and size, then the display quality is improved, but signal delay and distortion increase due to parasitic capacitance and resistance in gate lines
Solution Approach 1:
The gate driver is divided into multiple gate drivers (first gate driver and second gate driver) that are distributed across different sides of the pixel portion. Each gate driver independently controls specific gate lines, segmenting the signal transmission paths to reduce the impact of parasitic capacitance and resistance on any single path, thereby maintaining signal integrity in high-definition displays
2Device complexity
If gate drivers are provided close to one side of the pixel portion, then the device complexity is reduced, but the display portion becomes asymmetric and farther from one side than the other
Solution Approach 1:
The gate driver functionality is segmented into multiple independent gate drivers positioned at different locations (right side and left side of pixel portion). This segmentation allows the display to maintain geometric symmetry while keeping each individual gate driver configuration relatively simple
Solution Approach 2:
The patent intentionally introduces asymmetry in the functional distribution of gate drivers (first gate driver controlling odd-numbered lines, second gate driver controlling even-numbered lines) to achieve overall symmetry in the physical layout, balancing the asymmetric control functions across symmetric physical positions
3Length of stationary object
If signal transmission distance through gate lines is increased to cover larger display areas, then the display size is improved, but signal delay and distortion increase due to parasitic capacitance and resistance
Solution Approach 1:
The gate driver system is segmented into multiple distributed gate drivers, each responsible for specific regions and gate lines. This segmentation reduces the effective signal transmission distance for each driver, minimizing the cumulative effect of parasitic capacitance and resistance, thereby reducing signal delay and distortion across large display areas
Solution Approach 2:
Multiple gate drivers act as intermediary signal sources distributed across the display, reducing the transmission distance between the signal source and the pixels. This intermediary approach eliminates the need for long-distance signal transmission from a single gate driver, reducing the impact of parasitic effects
Data Source
AI summary
It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.