Dual Gate Electrode Fabrication for CMOS Devices
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Solution Overview
Problem
Conventional methods for fabricating CMOS semiconductor devices face challenges in achieving high impurity concentrations for PMOS and NMOS gate electrodes, leading to a poly-depletion effect that increases the effective thickness of the gate insulating layer and alters the threshold voltage.
Innovation Solution
A method involving the formation of a recessed semiconductor layer with a higher concentration of impurities in the upper region, followed by annealing to diffuse impurities and planarization, allowing for the creation of gate electrodes with improved impurity distribution and concentration, thereby preventing the poly-depletion effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type impurities are increased in the polysilicon layer to improve NMOS gate electrode properties, then the NMOS transistor performance is improved, but it becomes difficult to increase p-type impurity concentration in the PMOS transistor region, leading to poly-depletion effect and threshold voltage change
Solution Approach 1:
The polysilicon layer is divided into two distinct regions with different impurity concentrations: a first polysilicon layer region with high n-type impurity concentration for NMOS gate electrode, and a second polysilicon layer region with high p-type impurity concentration for PMOS gate electrode. This segmentation allows each region to be independently optimized for its respective transistor type, resolving the contradiction between improving NMOS performance and maintaining PMOS performance.
Solution Approach 2:
Different local regions of the polysilicon layer are given different impurity concentrations and types: the first region has high n-type impurity concentration while the second region has high p-type impurity concentration. This local quality differentiation enables each gate electrode region to have the optimal impurity characteristics for its specific transistor type, preventing poly-depletion effect in both regions.
2Ease of manufacture
If a single polysilicon layer is used for both PMOS and NMOS gate electrodes, then the fabrication process is simplified, but the impurity concentration cannot be sufficiently high for both transistor types, causing poly-depletion effect
Solution Approach 1:
The polysilicon layer is segmented into a first polysilicon layer and a second polysilicon layer with different impurity characteristics. The first polysilicon layer is doped with high concentration n-type impurities for NMOS, while the second polysilicon layer is doped with high concentration p-type impurities for PMOS. This segmentation maintains relative fabrication simplicity while achieving the reliability needed for both transistor types.
Solution Approach 2:
The solution transitions from a single-layer polysilicon structure to a multi-layer polysilicon structure, adding a vertical dimension to the impurity concentration control. By creating distinct polysilicon layer regions at different locations, the patent achieves high impurity concentrations for both transistor types without significantly complicating the overall fabrication process.
3Reliability
If p-type impurities are ion-implanted into the polysilicon layer to create PMOS gate electrode, then the PMOS transistor region gains p-type characteristics, but the concentration is limited by the existing n-type impurity concentration and the polysilicon layer's saturation limit
Solution Approach 1:
The polysilicon layer is segmented so that the second polysilicon layer region can be independently doped with p-type impurities without being constrained by the n-type impurity concentration in the first region. This segmentation removes the limitation where high n-type impurity concentration prevented adequate p-type impurity incorporation, allowing the PMOS gate electrode region to achieve the necessary high p-type impurity concentration.
Solution Approach 2:
The second polysilicon layer region is given local quality with high p-type impurity concentration specifically where the PMOS gate electrode is formed. This localized quality enhancement allows the PMOS region to achieve sufficient p-type doping levels without being affected by the n-type impurity concentration elsewhere in the polysilicon structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in CMOS semiconductor devices with improved transistor properties by maintaining high impurity concentrations in the gate electrodes, reducing the poly-depletion effect and enhancing the performance of NMOS and PMOS transistors.
Implementation Method 1
impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region
Implementation Method 2
The first and second semiconductor layers are annealed
Implementation Method 3
annealing to diffuse impurities
Data Source
AI summary
In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form a recessed semiconductor layer that is thinner than the initial semiconductor layer. Impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region, respectively. Then, the first and second semiconductor layers are annealed, and the annealed first semiconductor layer is planarized. The resulting structure may be etched to form gate electrodes that are capable of having high concentrations of impurities.