Dual-Gate Electrode Impurity Diffusion Control
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Solution Overview
Problem
As semiconductor devices miniaturize, variations in gate dimensions and mutual diffusion of impurities at the PN boundary in CMIS dual-gate structures lead to inconsistencies in transistor characteristics, particularly affecting SRAMs, causing variations in threshold voltage and potentially leading to circuit failures.
Innovation Solution
The semiconductor device incorporates a dual-gate electrode structure with specific impurity concentrations and isolation widths to minimize variations in gate dimensions and impurity diffusion, achieved through precise masking and impurity implantation techniques during fabrication, ensuring consistent impurity profiles and reduced etching speed differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ions of impurities are implanted into polysilicon film for gate electrodes using a mask designed such that the boundary between n-type region and p-type region is located on an isolation between well regions, then the gate electrode can be formed with dual-gate structure, but impurities diffuse from one region to the other through the metal silicide layer or polysilicon film, resulting in work function change and threshold voltage variation
Solution Approach 1:
An insulating film is introduced as an intermediary layer between the n-type and p-type polysilicon gate electrode regions. This insulating film prevents direct contact and impurity diffusion between the doped regions, thereby maintaining stable work functions and consistent threshold voltages while still allowing the dual-gate structure to function. The insulating film acts as a barrier that mediates the interaction between the n-type and p-type regions.
Solution Approach 2:
The problematic metal silicide layer that causes impurity diffusion is removed or avoided in the boundary region between n-type and p-type gate electrodes. By extracting the metal silicide layer from the critical boundary area, the patent eliminates the diffusion pathway for impurities while maintaining the electrical connectivity function through alternative means.
2Productivity
If the integration degree of semiconductor integrated circuits is increased by miniaturizing CMIS devices with dual-gate structures, then device density improves, but variations in gate dimensions and impurity diffusion at PN boundary increase, leading to transistor characteristic inconsistencies
Solution Approach 1:
The insulating film serves as a mediator that stabilizes the PN boundary region in miniaturized devices. By preventing impurity diffusion at the boundary, it ensures consistent transistor characteristics even as device dimensions are reduced and integration density is increased.
Solution Approach 2:
The patent applies different properties to different regions: the insulating film is specifically placed at the boundary region between n-type and p-type gate electrodes, while the bulk regions maintain their respective doped characteristics. This local differentiation allows the boundary region to have improved stability without compromising the overall device performance.
3Reliability
If metal silicide layer is formed on polysilicon gate electrode to connect n-type and p-type polysilicon gate electrodes, then electrical connectivity is achieved, but impurity diffusion through the metal silicide layer causes work function change
Solution Approach 1:
The insulating film acts as an intermediary barrier that prevents impurity diffusion through the metal silicide layer while allowing the metal silicide to maintain its electrical connectivity function. The insulating film is positioned such that it blocks the diffusion pathway without interfering with the electrical connection between gate electrodes.
Solution Approach 2:
The gate electrode structure is segmented into distinct regions: n-type polysilicon region, insulating film barrier, p-type polysilicon region, and metal silicide connectivity layer. This segmentation separates the electrical connectivity function (metal silicide) from the impurity diffusion pathway, allowing each to perform its intended function independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variations in transistor characteristics by controlling impurity concentrations and isolation widths, enhancing the reliability and performance of CMIS dual-gate structures, particularly in SRAMs, by minimizing the impact of impurity diffusion and etching speed variations.
Implementation Method 1
a first insulating film for preventing diffusion of impurities between the n-type polysilicon gate electrode region and the p-type polysilicon gate electrode region
Implementation Method 2
a metal silicide layer formed on the polysilicon gate electrode in order to connect an n-type polysilicon gate electrode and a p-type polysilicon gate electrode
Implementation Method 3
ions of impurities are implanted into the polysilicon film for gate electrodes using a mask
Data Source
AI summary
A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.