Dual-Gate Ferroelectric Memory for Linear Conductance
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Solution Overview
Problem
Current neuromorphic processors face challenges in achieving linear response characteristics for pattern recognition, which is crucial for efficient neural network operations, due to non-linear changes in conductance caused by gate voltages.
Innovation Solution
A ferroelectric memory device is designed with a channel layer, two gate electrodes, and a ferroelectric layer, where different voltages can be independently applied to each gate electrode, improving the linearity of conductance changes by combining pulse and DC voltages, and optimizing the materials and structures for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate electrode is used in a memory cell, then the device structure is simple, but the conductance change response to gate voltage is non-linear
Solution Approach 1:
The single gate electrode is divided into two separate gate electrodes (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows independent adjustment of voltages applied to each gate, enabling linearization of the overall conductance response through coordinated voltage control while maintaining relatively simple individual gate structures
2Manufacturing precision
If different voltages are applied to two gate electrodes to improve linearity, then the conductance response becomes linear, but the device operation becomes more complex
Solution Approach 1:
The voltage control system applies periodic pulse voltages to the first gate electrode and complementary DC or pulse voltages to the second gate electrode. This periodic action pattern simplifies the control logic by establishing a predictable voltage application sequence, making it easier to manage the dual-gate system while achieving linear conductance modulation
3Device complexity
If conventional memory structures are used, then the device structure is simple, but power consumption is high and area is large
Solution Approach 1:
The memory cell utilizes ferroelectric material properties and dual-gate voltage control to dynamically adjust conductance states. By changing the voltage parameters applied to the two gates independently, the device achieves better area efficiency and power consumption characteristics while maintaining non-volatile memory functionality, overcoming the limitations of conventional single-gate structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ferroelectric memory device achieves improved linearity in conductance changes, enhancing pattern recognition rates and reducing power consumption, making it suitable for neuromorphic processors and neural network operations.
Implementation Method 1
a ferroelectric layer between the channel layer and the first gate electrode and the ferroelectric layer may be between the channel layer and the second gate electrode
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C
AI summary
A ferroelectric memory device may include a source, a drain, a channel layer between the source and the drain and connected to the source and the drain, a first gate electrode and a second gate electrode located on the channel layer to be spaced apart from each other, and a ferroelectric layer between the channel layer and the first gate electrode and between the channel layer and the second gate electrode. Different voltages may be applied to the first gate electrode and the second gate electrode.