Dual Gate Stack Dielectric Profile for Void-Free Gap Fill
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the reduction in minimum feature size leads to issues such as voids in dielectric material, which can be filled with undesirable materials, affecting the gap fill window and device performance.
Innovation Solution
Widening the upper portion of the opening in the dielectric material gap fill window using one or more cycles of treatment and etching processes, such as atomic layer etch, to reduce voids and maintain effective gate width, thereby improving manufacturing defects and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but voids form in the dielectric material affecting gap fill window and device performance
Solution Approach 1:
The opening is divided into two distinct portions: a first portion with a first width and a second portion with a second width that is greater than the first width. This segmentation allows the dielectric material to be deposited with different dimensional requirements in different regions, enabling complete gap filling without voids while maintaining the miniaturized feature size for high integration density
Solution Approach 2:
The opening geometry is changed from a uniform cross-section to a tapered or non-uniform cross-section where the width varies along the depth. This dimensional change creates a favorable deposition geometry that eliminates void formation while preserving the small lateral dimensions needed for high integration density
2Reliability
If the opening width is reduced to maintain effective gate width, then transistor performance is maintained, but voids form in the dielectric material
Solution Approach 1:
The opening is segmented into an upper portion and a lower portion with different width characteristics. The upper portion has a larger width that facilitates complete dielectric material deposition without voids, while the lower portion maintains a smaller width that preserves the effective gate width for optimal transistor performance
Solution Approach 2:
Different portions of the opening are given different width characteristics suited to their specific functions. The upper portion is widened locally to enable defect-free dielectric filling, while the lower portion maintains its narrow dimensions locally to preserve gate effectiveness, allowing each region to optimize for its specific requirement
3Manufacturing precision
If the opening is widened to improve dielectric material gap fill, then voids are reduced, but effective gate width is compromised
Solution Approach 1:
The opening width is segmented such that only the upper portion is widened to improve gap fill quality, while the lower portion near the gate maintains its original narrow width. This ensures complete dielectric filling without voids while preserving the effective gate width critical for transistor performance
Solution Approach 2:
The opening geometry is transformed from a uniform width to a tapered geometry where the width increases in the upper portion. This dimensional change improves dielectric material deposition and void elimination while the lower portion near the gate maintains the narrow dimensions needed for effective gate width
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the gap fill window of the dielectric material, reduces manufacturing defects, and improves device performance by ensuring effective separation of metal gates in adjacent transistors.
Implementation Method 1
Widening the upper portion of the opening in the dielectric material gap fill window using one or more cycles of treatment and etching processes, such as atomic layer etch
Data Source
AI summary
A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.