Dual-Gate GaN HEMT Suppressing Current Collapse

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Solution Overview

Problem

Group III nitride semiconductor HEMT devices experience a 'current collapse' phenomenon, where the output current of the drain electrode fails to keep up with gate control signal changes, leading to significant turn-on transient delays, especially under high current and high voltage conditions, due to the virtual gate model and surface state charge accumulation.

Innovation Solution

A laminated dual-gate structure is implemented, where the two-dimensional electron gas is regulated by the interaction between a top gate and a main gate, with a dielectric layer and a plasma processing region to control the channel electron concentration, allowing the output current to synchronize with gate voltage changes and reduce current collapse effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional single-gate HEMT structure is used, then the device structure is simple, but the output current cannot keep up with gate control signal changes, causing current collapse and turn-on transient delay

Engineering Contradiction:
Improvecurrent response speedVSAvoidgate structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The gate structure is segmented into two independent gates: a main gate and a top gate. The main gate controls the overall channel conduction, while the top gate specifically regulates the 2DEG concentration in the channel. This segmentation allows independent optimization of each gate's function, enabling fast current response without excessive overall complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The top gate is positioned in the vertical dimension above the main gate, creating a three-dimensional gate configuration. This vertical stacking adds a new control dimension without significantly increasing lateral footprint, allowing the top gate to exert electrostatic influence on the 2DEG channel from above while maintaining a compact device layout

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If surface treatment is performed to reduce surface state density, then surface state charge accumulation is reduced, but the effect is not ideal under high current and high voltage conditions

Engineering Contradiction:
Improvecurrent collapse suppressionVSAvoidhigh current and high voltage performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The top gate acts as an intermediary control element between the control circuit and the 2DEG channel. By applying appropriate voltage to the top gate, the 2DEG concentration can be precisely regulated, and the harmful virtual gate effect from surface states can be counteracted, improving reliability under high current and voltage conditions

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The top gate enables dynamic adjustment of the 2DEG concentration parameter in the channel. By changing the top gate voltage, the electron concentration can be optimized for different operating conditions, allowing the device to maintain high reliability across a wide range of current and voltage levels

Inventive Principle:
Principle #35Parameter changes

3Strength

If a field plate structure is used to reduce electric field strength, then gate-drain and gate-source breakdown is prevented, but current collapse is not effectively suppressed

Engineering Contradiction:
Improvebreakdown resistanceVSAvoidcurrent collapse suppression
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The gate structure is segmented into two independent gates: a main gate and a top gate. The main gate controls the overall channel conduction, while the top gate specifically regulates the 2DEG concentration in the channel. This segmentation allows independent optimization of each gate's function, enabling fast current response without excessive overall complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The top gate is positioned in the vertical dimension above the main gate, creating a three-dimensional gate configuration. This vertical stacking adds a new control dimension without significantly increasing lateral footprint, allowing the top gate to exert electrostatic influence on the 2DEG channel from above while maintaining a compact device layout

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dual-gate structure effectively suppresses current collapse by ensuring timely induction and release of two-dimensional electron gas, reducing dynamic turn-on resistance and delay time, thereby enhancing the device's high-frequency and high-power switching performance.

Implementation Method 1

the two-dimensional electron gas with a high concentration can be formed in the heterostructure, such as AlGaN/GaN, due to the piezoelectric polarization and spontaneous polarization effect

Methodology Applied
Scientific EffectPiezoelectric polarization: Piezoelectric Effect

Implementation Method 2

the two-dimensional electron gas with a high concentration can be formed in the heterostructure, such as AlGaN/GaN, due to the piezoelectric polarization and spontaneous polarization effect

Methodology Applied
Scientific EffectSpontaneous polarization:

Implementation Method 3

the charge in the virtual gate cannot be timely released. The concentration of channel electron under the gate is low, so the output current at the drain end is small

Methodology Applied
Scientific EffectElectrostatic induction: Electrostatic Induction

Data Source

PatentUS9070756B2Group III nitride high electron mobility transistor (HEMT) device
Publication Date: 2015.06.30 SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
  • US9070756B2 patent drawing
  • US9070756B2 patent drawing
  • US9070756B2 patent drawing

AI summary

A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode (112), a drain electrode (111), a main gate (116), a top gate (118), an insulating dielectric layer (117) and a heterostructure, wherein the source electrode (112) and the drain electrode (111) are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor (113) and a second semiconductor (114); the first semiconductor (113) is disposed between the source electrode (112) and drain electrode (111); the second semiconductor (114) is formed on the surface of the first semiconductor (113) and is provided with a band gap wider than the first semiconductor (113); the main gate (116) is disposed at the side of the surface of the second semiconductor (114) adjacent to the source electrode (112), and is in Schottky contact with the second semiconductor (114); the dielectric layer (117) is disposed on the surfaces of the second semiconductor (114) and the main gate (116) and between the source electrode (112) and the drain electrode (111); the top gate (118) is formed on the surface of the dielectric layer (117), at least one side edge of the top gate extends towards the direction of the source electrode (112) or the drain electrode (111), and the orthographic projection of the top gate overlaps with the two side edges of the main gate (116). When the HEMT device is at work, the main gate (116) and the top gate (118) are respectively controlled by a control signal. The device can effectively inhibit the “current collapse effect”.