Dual-Gate HEMT Structure for Threshold Voltage Separation
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Solution Overview
Problem
Existing high electron mobility transistors (HEMTs) face issues with process-induced performance reduction and non-uniformity, particularly in the transition from normally-off to normally-on types, which affect their electric performance and reliability.
Innovation Solution
A semiconductor device integrating a normally-off HEMT and a normally-on HEMT with different gate electrode lengths in a passivation layer, where the stress of the passivation layer on the first gate electrode is compressive, adjusting the threshold voltage to achieve a normally-off function, while the second gate electrode is not affected by compressive stress to maintain a normally-on function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single gate electrode structure is used in HEMT fabrication, then the manufacturing process is simple, but the threshold voltage cannot be adjusted to achieve both normally-off and normally-on functions
Solution Approach 1:
The gate electrode is divided into two separate gate electrodes (first gate electrode and second gate electrode) with different gate lengths, allowing independent control of threshold voltage for normally-off and normally-on HEMT functions while maintaining structural simplicity
Solution Approach 2:
Different regions of the gate structure are designed with different gate lengths (first gate length and second gate length) to create local variations in electric field distribution, enabling threshold voltage adjustment for different HEMT types in different regions
2Manufacturing precision
If etching processes are used to adjust threshold voltage in HEMTs, then threshold voltage control is achieved, but process-induced damage and non-uniformity increase
Solution Approach 1:
The threshold voltage adjustment is achieved through preliminary design of different gate lengths in the gate electrode structure, which determines the electric field distribution and threshold voltage before any etching or doping processes, thereby avoiding process-induced damage and non-uniformity
3Strength
If gate length is increased to improve breakdown voltage, then breakdown voltage increases, but switching speed decreases
Solution Approach 1:
The gate is segmented into two electrodes with different gate lengths: a longer first gate electrode for high breakdown voltage and a shorter second gate electrode for fast switching, allowing both requirements to be satisfied simultaneously in different regions of the device
Solution Approach 2:
Different gate length dimensions are assigned to different gate electrodes based on local functional requirements: the first gate electrode has a longer gate length for breakdown voltage strength, while the second gate electrode has a shorter gate length for switching speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and performance of the semiconductor device by maintaining the threshold voltage difference between the two types of HEMTs, reducing damage from etching processes, and improving the breakdown voltage and switching speed.
Implementation Method 1
the stress of the passivation layer applying to a first gate electrode is different from the stress of the passivation layer applying to a second gate electrode, thereby adjusting the threshold voltage
Data Source
AI summary
A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A passivation layer covers the semiconductor barrier layer. A first gate electrode and a second gate electrode are laterally separated from each other and at least partially disposed in the passivation layer respectively. Along a first direction, a first gate length of the first gate electrode is less than a second gate length of the second gate electrode. A source electrode and a drain electrode are disposed on the semiconductor channel layer. The second gate electrode is electrically connected to the source electrode. The first gate electrode and the second gate electrode are electrically isolated from each other.