Dual-Gate Semiconductor Structure With Local Insulator Thinning
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Solution Overview
Problem
Existing semiconductor devices with bottom-gate transistors face challenges such as increased manufacturing steps and reduced functionality of the back gate electrode due to the use of a thick planarization insulating layer, which hinders effective control of threshold voltage and on-state current.
Innovation Solution
A semiconductor device design that includes a first and second gate electrode with a thinner insulating layer between them, where the second gate electrode functions as a back gate electrode, allowing for reduced manufacturing steps and improved control of threshold voltage and on-state current, using a half-tone mask or gray-tone mask to vary the insulating layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a thick planarization insulating layer is formed over the transistor to increase aperture ratio or reduce noise, then the aperture ratio and noise performance are improved, but the back gate electrode cannot function well due to reduced electric field strength
Solution Approach 1:
The insulating layer is segmented into two distinct layers: a first insulating layer between the back gate electrode and semiconductor layer, and a second insulating layer (planarization layer) over the semiconductor layer. This segmentation allows the first layer to maintain thin thickness for effective back gate control while the second layer provides the necessary planarization and noise reduction, resolving the contradiction between aperture ratio and back gate functionality.
Solution Approach 2:
Different regions of the insulating structure are assigned different thicknesses and functions: the first insulating layer is kept thin locally beneath the back gate electrode to maintain electric field strength, while the second insulating layer is made thick in regions where planarization is needed but does not interfere with gate control, achieving both aperture ratio improvement and back gate functionality.
2Ease of manufacture
If the back gate electrode and pixel electrode are formed using the same layer to reduce manufacturing steps, then the number of manufacturing steps is reduced, but the planarization insulating layer thickness prevents effective back gate control
Solution Approach 1:
The insulating layer is divided into a first insulating layer and a second insulating layer with different thicknesses and functions. The first insulating layer is positioned to allow back gate electrode functionality, while the second provides planarization. This segmentation enables both manufacturing efficiency and precise threshold voltage control through the back gate.
Solution Approach 2:
The insulating structure exhibits local quality variations where the first insulating layer is thin in the region between the back gate electrode and semiconductor layer to enable effective control, while the second insulating layer provides thicker planarization in other regions. This local differentiation achieves both ease of manufacture and manufacturing precision.
3Shape
If a thick insulating layer is used between the back gate electrode and semiconductor layer to provide planarization, then planarization is improved, but the on-state current decreases due to reduced electric field control
Solution Approach 1:
The insulating layer is segmented into a first insulating layer with small thickness for effective electric field control and a second insulating layer for planarization. This segmentation ensures that the first layer maintains strong electric field coupling between the back gate electrode and semiconductor layer, preserving on-state current, while the second layer provides the necessary planarization surface.
Solution Approach 2:
The insulating structure has different thickness characteristics in different regions: the first insulating layer is thin locally to maintain electric field strength and on-state current, while the second insulating layer provides thick planarization in regions where it does not interfere with gate control, achieving both planarization quality and power performance.
Data Source
AI summary
A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.