Dual-Gate Junction FET Integration for Lower On-Resistance
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Solution Overview
Problem
Conventional integration of junction field-effect transistors into BiCMOS processes results in excessively high off-voltages and on-resistances due to the requirement of extra masks and implantation steps.
Innovation Solution
A structure and method for forming a junction field-effect transistor with a first gate on the semiconductor substrate's top surface and a second gate beneath it, along with a channel region between them, which eliminates the need for additional masks and optimizes the transistor's performance by reducing on-resistance through shared processing steps with bipolar junction transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional integration methods are used, then junction field-effect transistors can be integrated into BiCMOS process, but off-voltages become excessively high and on-resistances become excessively high
Solution Approach 1:
The gate structure is divided into two separate gates: a first gate positioned above the semiconductor substrate and a second gate positioned beneath the substrate. This segmentation allows independent optimization of gate control, enabling reduced on-resistance through enhanced channel modulation while maintaining appropriate off-voltage levels, thereby resolving the performance degradation caused by conventional single-gate integration
Solution Approach 2:
The invention extends the gate control from a single-plane configuration to a three-dimensional arrangement by placing gates on opposite sides of the semiconductor substrate. This dimensional change enables superior electric field distribution and channel control, achieving lower on-resistance without sacrificing off-voltage characteristics
2Adaptability or versatility
If extra masks and implantation steps are added, then junction field-effect transistors can be formed, but device complexity and manufacturing steps increase
Solution Approach 1:
The formation of the dual-gate junction field-effect transistor is merged with existing BiCMOS fabrication sequences. The first gate is integrated during front-end processing alongside bipolar transistor formation, while the second gate is formed during back-end processing, eliminating the need for separate dedicated fabrication steps and reducing overall process complexity
Solution Approach 2:
The fabrication process is designed to serve multiple functions: the same processing steps that form bipolar junction transistors also create the first gate of the junction field-effect transistor, and subsequent steps simultaneously complete both device types. This multi-functionality eliminates redundant masks and implantation steps while maintaining integration capability
Data Source
AI summary
Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.