Dual-Gate LNA Semiconductor Structure for Stable Gain
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Solution Overview
Problem
Low noise amplifiers (LNAs) in RF front-end circuits face instability due to hole accumulation in the common region shared by common source and common gate circuits, leading to destabilization of the transistor operation and reduced gain.
Innovation Solution
A semiconductor device with a dual gate configuration that connects a common region and a body region, allowing different lengths for the gate electrodes of the common source and common gate circuits, thereby increasing resistance and stabilizing current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a common region is shared by common source circuit and common gate circuit to reduce noise, then noise reduction is achieved, but hole accumulation destabilizes transistor operation and reduces gain
Solution Approach 1:
The patent divides the common region into multiple segmented regions (first common region, second common region, third common region) separated by insulating portions. This segmentation prevents hole accumulation from destabilizing the entire common region while maintaining noise reduction benefits through controlled current paths.
Solution Approach 2:
The patent introduces a body region as an intermediary element between the common region and substrate, along with connection regions that selectively connect common regions to the body region or substrate. This intermediary structure controls hole flow and stabilizes transistor operation while preserving the shared common region's noise reduction function.
2Reliability
If gate electrode lengths are made different to optimize circuit performance, then gain is improved, but device complexity increases
Solution Approach 1:
The patent applies different gate electrode lengths (first gate electrode, second gate electrode, third gate electrode) to different transistor regions based on their specific performance requirements. This local differentiation optimizes gain for each circuit section without requiring complete redesign of the entire device structure.
Solution Approach 2:
The patent employs asymmetric gate electrode configurations where the first gate electrode has a different length than the second and third gate electrodes. This asymmetric design allows independent optimization of common source and common gate circuit performance, achieving higher overall gain while maintaining a relatively simple unified structure.
3Reliability
If resistance between common region and drain region is increased to enhance gain, then gain is improved, but current flow stability may be affected
Solution Approach 1:
The patent introduces the body region as an intermediary between the common region and substrate, with controlled connection regions that regulate current flow. This intermediary structure increases resistance between the common region and drain region to enhance gain while simultaneously stabilizing current flow through the body region's moderating effect.
Solution Approach 2:
The patent modifies the electrical parameters of the common region by introducing insulating portions that segment the region and alter resistance characteristics. This changes the current flow paths and resistance values to achieve both higher gain and stable operation by controlling hole accumulation and distribution.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate including first and second regions and a third region between the first and second regions, a first gate electrode of a first transistor extending along a first direction on the third region, a second gate electrode of a second transistor spaced apart from the first gate electrode in a second direction on the third region and extending along the first direction, a first common region extending from the third region to the first region and disposed between the first gate electrode and the second gate electrode, a first body region extending from the third region to the first region and disposed below the second gate electrode, a first insulating portion between the first common region and the first body region in the first region and a connection region connecting the first common region and the first body region.