Dual-Gate LTPS TFTs Reducing Feed-Through Voltage
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Solution Overview
Problem
Conventional LTPS TFTs experience leakage current and parasitic capacitance issues due to the limited masking effect of the light shielding layer, leading to feed-through voltage, which affects TFT performance.
Innovation Solution
The implementation of a low-temperature poly silicon thin film transistor (LTPS TFT) with two gates, where the first gate and second gate are applied with opposite voltages, and are at least partially overlapped, along with a polysilicon layer covering the substrate, a gate insulation layer, and a passivation layer, to reduce feed-through voltage and enhance TFT performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a metallic light shielding layer is plated above the glass substrate to prevent leakage current, then the masking effect is improved, but parasitic capacitance is generated between the light shielding layer and other conductive layers causing feed through voltage
Solution Approach 1:
The patent extracts the light shielding function from a separate metallic layer and integrates it into the polysilicon layer itself. The polysilicon layer is configured to perform both the transistor channel function and the light shielding function, eliminating the need for a separate metallic light shielding layer that would generate parasitic capacitance.
Solution Approach 2:
The polysilicon layer is designed to serve multiple functions simultaneously: it acts as the active channel of the TFT and also provides light shielding. This multi-functionality approach consolidates what were previously separate components, reducing the total number of layers and interfaces that could generate parasitic capacitance.
2Illumination intensity
If the light shielding layer and other conductive layers are placed close together, then the masking effect is maintained, but feed through voltage occurs due to parasitic capacitance
Solution Approach 1:
The patent removes the separate metallic light shielding layer that was causing feed through voltage issues. By extracting this function and integrating it into the polysilicon layer, the patent eliminates the parasitic capacitance problem while maintaining the necessary light shielding effect.
Solution Approach 2:
The patent merges the light shielding function with the polysilicon layer, combining what were previously separate functional elements. This consolidation eliminates the interface between the light shielding layer and other conductive layers, thereby eliminating the source of parasitic capacitance and feed through voltage.
Data Source
AI summary
A LTPS TFT and a TFT substrate are disclosed. The LTPS TFT includes: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, and the polysilicon layer covers the first gate, wherein the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the LTPS TFT has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage. In this way, the feed through voltage may be reduced such that the TFT performance is enhanced.