Dual-Gate Memory Cell Structure for Low-Leakage Data Retention
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Solution Overview
Problem
Conventional DRAMs face challenges such as high leakage current, complex manufacturing processes, high costs, and poor scalability due to their dynamic nature and complex control circuits, limiting their performance and reliability as memory technology approaches physical limits.
Innovation Solution
A memory structure is designed with a channel body, source and drain regions, and dual gate structures that function like a thyristor, improving reliability, retention time, and power consumption, allowing for enhanced scalability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM structure is used, then memory capacity can be achieved, but leakage current increases and reliability deteriorates
Solution Approach 1:
The channel body is segmented into multiple regions with different conductivity types (first conductivity type and second conductivity type), creating a multi-region channel structure that reduces leakage current while maintaining memory functionality
Solution Approach 2:
Different regions of the channel body are assigned different conductivity types and doping concentrations, creating localized properties that optimize both leakage reduction in certain regions and carrier injection in others
2Area of moving object
If memory structure is shrunk in size, then capacity increases, but manufacturing complexity and cost increase
Solution Approach 1:
The memory cell is divided into distinct functional regions (source region, drain region, channel body with multiple conductivity regions) that can be formed through systematic processing steps, enabling scaling while managing manufacturing complexity
Solution Approach 2:
The patent introduces vertical stacking with gate structures positioned at different heights (first gate structure and second gate structure), transitioning from planar to three-dimensional architecture to reduce footprint without proportionally increasing manufacturing complexity
3Ease of operation
If dynamic memory cell structure is used, then random access capability is achieved, but power consumption increases
Solution Approach 1:
The patent utilizes changes in conductivity type and carrier concentration in different channel regions to enable memory operation, replacing the need for continuous refresh operations with parameter-based control that reduces power consumption
4Device complexity
If control circuit is simplified, then manufacturing cost decreases, but scalability is reduced
Solution Approach 1:
The multi-region channel structure with dual gate configurations serves multiple functions simultaneously: it provides memory storage capability, enables scalability through systematic expansion, and maintains manufacturing feasibility through standardized processing steps
Data Source
AI summary
A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.