Dual Gate MOSFET Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor technology is to reduce parasitic gate capacitance in MOSFET and finFET devices while scaling down device dimensions, as increasing gate length improves control but leads to high parasitic capacitance and poor performance in high-frequency applications.
Innovation Solution
Implementing a dual gate structure with a first gate above the channel region and a second gate above the drift region, electrically decoupled from the first gate, which can be biased at different voltage levels, reducing parasitic capacitance and allowing self-aligned source/drain formation without additional fabrication steps or masking layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate length is increased to improve control of channel region, then device reliability is improved, but parasitic gate capacitance increases and high-frequency performance deteriorates
Solution Approach 1:
The gate structure is divided into two separate gates: a first gate over the channel region and a second gate over the drift region. This segmentation allows each gate to be independently controlled and optimized, reducing the overall parasitic capacitance while maintaining control over the channel region.
Solution Approach 2:
The second gate structure is extracted and positioned over the drift region, electrically decoupled from the first gate. This extraction separates the control functions, allowing the first gate to focus on channel control while the second gate manages the drift region, thereby reducing parasitic capacitance between gate and drain.
2Productivity
If device dimensions are scaled down to reduce footprint and improve performance, then productivity is improved, but parasitic capacitance control becomes more difficult
Solution Approach 1:
The patent transitions from a planar gate structure to a vertical/dual-layer gate configuration. The first gate is positioned over the channel region while the second gate is positioned over the drift region in a vertically stacked or laterally separated arrangement, utilizing three-dimensional space to reduce parasitic capacitance while maintaining compact footprint.
Data Source
AI summary
The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.