Dual-Gate MOSFET Drive Circuit for Faster Switching
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Solution Overview
Problem
Traditional power MOSFETs have high Miller capacitance, leading to slow switching speed, and high on-resistance, resulting in high power consumption.
Innovation Solution
A gate drive circuit for power semiconductor devices with separate first and second gates, where the first gate controls the channel region and the second gate controls the drift region, optimizing the timing of voltage connections to reduce Miller capacitance and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional power MOSFET structure is used, then device simplicity is maintained, but Miller capacitance increases leading to slow switching speed
Solution Approach 1:
The gate structure is divided into two independent gates: first gate connected to channel region and second gate connected to drift region. This segmentation allows independent control of channel formation and drift region characteristics, enabling reduced Miller capacitance through optimized gate timing while maintaining device functionality.
Solution Approach 2:
The patent introduces a temporal dimension to gate control by sequentially activating first gate then second gate during switching operations. This time-based control strategy enables dynamic optimization of transistor characteristics during different switching phases, achieving faster switching speeds without compromising device simplicity.
2Use of energy by moving object
If traditional single-gate control is used, then device complexity is low, but on-resistance increases leading to high power consumption
Solution Approach 1:
The gate control function is segmented into two independent gate drivers that can be activated sequentially. First gate driver controls channel region for current conduction, while second gate driver controls drift region for resistance optimization. This segmentation enables reduced on-resistance and power consumption through coordinated gate timing.
Solution Approach 2:
The first gate is activated in advance to form the conductive channel before the second gate is activated to optimize the drift region. This preliminary action ensures that the channel is already formed when the drift region characteristics are optimized, minimizing total on-resistance and reducing power consumption during conduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves switching speed and reduces on-resistance, thereby decreasing power consumption of the transistors.
Implementation Method 1
the first gate is disposed above a channel region of the transistor and is configured to control the channel region
Implementation Method 2
the second gate is disposed above a field oxide of the transistor and is configured to control a drift region of the transistor; the second gate controls the drift region of the transistor to form an accumulation layer
Implementation Method 3
the traditional power MOSFET, when in use, has a relatively large Miller capacitance, resulting in a relatively slow switching speed
Data Source
AI summary
A gate drive circuit for a power semiconductor device, a low-side switching circuit, a high-side switching circuit, and a drive method are disclosed. When a first gate driver receives a control signal which is at a first level, the first gate driver connects a first gate to a first voltage, so that the first gate controls a channel region. When the transistor operates on a Miller plateau, the area of an overlapping region between the first gate and a drain inside the transistor is relatively small, so the Miller capacitance of the transistor is relatively small, thereby improving the switching speed of the transistor. A second gate is connected to a second voltage after a first duration, so that the second gate controls a drift region of the transistor to form an accumulation layer, and the accumulation layer has a relatively high carrier concentration.