Dual-Gate NOR Memory Cell Array With Increased Source-Bias Voltage
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Solution Overview
Problem
NOR-type memory arrays face background leakage issues due to leakage currents in unselected memory cells, which can lead to read operation failures, and existing solutions like raising threshold voltage or applying negative gate bias voltage either result in unsatisfactory drain currents or increase chip area and cost.
Innovation Solution
Applying the same increment in bias voltage to all word lines, source lines, and bit lines in a NOR-type memory array, combined with dual-gate transistors to maintain transistor functionality and suppress leakage currents without negative bias voltage, thereby increasing threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If negative gate bias voltage is applied to suppress leakage currents, then leakage current is reduced, but additional power sources are required increasing device complexity
Solution Approach 1:
The patent extracts and eliminates the need for negative bias voltage generation circuitry by reconfiguring the memory array to use only positive voltage rails. The word lines are connected to a positive voltage rail instead of requiring separate negative voltage generation, removing the harmful dependency on additional power sources while maintaining leakage suppression through alternative means.
Solution Approach 2:
The patent changes the voltage parameter configuration by introducing an odd number of string groups with alternating connections to positive and negative voltage rails. This parameter change allows the system to achieve leakage current suppression through the inherent voltage distribution across the memory strings without requiring active negative bias voltage generation circuitry.
2Object-generated harmful factors
If threshold voltage is raised to suppress leakage currents, then leakage current is reduced, but drain current becomes unsatisfactory
Solution Approach 1:
The patent applies local quality by creating different voltage conditions for different parts of the memory array. Through the odd-numbered string group configuration with alternating voltage rail connections, specific memory strings experience enhanced voltage differentials that suppress leakage locally, while selected strings maintain optimal drain current for reliable operation during read/write cycles.
Solution Approach 2:
The patent introduces dynamic voltage switching where the effective voltage across memory cells changes based on selection status. Unselected strings benefit from the inherent voltage distribution that suppresses leakage, while selected strings receive appropriate voltage boosts during operations to maintain satisfactory drain current, achieving both goals through time-varying voltage conditions.
3Quantity of substance
If more memory cells are integrated into a given area, then integration density is improved, but background leakage from unselected cells increases
Solution Approach 1:
The patent segments the memory array into an odd number of string groups with alternating connections to different voltage rails. This segmentation allows unselected memory strings to be naturally isolated through the voltage configuration, reducing background leakage from unselected cells while maintaining high integration density through efficient use of the memory array structure.
Data Source
AI summary
A method includes: providing a plurality of memory cells arranged in rows and a columns, wherein each of the plurality of memory cells comprises a dual-gate transistor, the dual-gate transistor comprising a silicon substrate, a channel layer over the silicon substrate, a first gate structure under the channel layer, and a second gate structure over the channel layer; providing a plurality of word lines extending in a first direction and electrically connected to the rows, respectively, and wherein the first gate structure and the second gate structure of the dual-gate transistor of each of the plurality of memory cells are electrically connected to one of the word lines; providing a plurality of source lines extending in a second direction and electrically connected to the columns, respectively; and providing a plurality of bit lines extending in the second direction and electrically connected to the columns, respectively.