Dual-Gate Semiconductor Structure for Lower On-Resistance
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Solution Overview
Problem
Semiconductor structures face challenges in reducing on-resistance (Ron) to enhance electrical performance, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor structure design featuring a substrate with a first and second dielectric layer, where the second gate is positioned on a recessed second dielectric layer with a conductive spacer and a hard mask layer, and a stop layer on the first gate, ensuring the bottom surfaces of the gates are on different planes, thereby reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-gate structures are used, then device simplicity is maintained, but on-resistance cannot be sufficiently reduced
Solution Approach 1:
The gate structure is segmented into a first gate and a second gate with different bottom surface heights, allowing each gate to independently control different regions of the semiconductor channel. This segmentation enables reduced on-resistance through optimized charge distribution while maintaining manageable device complexity through modular design
Solution Approach 2:
The invention transitions from a conventional planar single-gate structure to a three-dimensional dual-gate structure where the second gate is positioned at a different height level (different plane) than the first gate. This dimensional change allows for enhanced electrical performance by controlling the channel from multiple spatial perspectives without excessive complexity increase
2Reliability
If multiple gates at different heights are implemented, then on-resistance is reduced, but manufacturing process complexity increases
Solution Approach 1:
A stop layer is formed on the first gate before forming the second gate structure, establishing a predetermined height reference in advance. This preliminary action guides subsequent manufacturing steps to achieve the desired different-plane configuration while simplifying the overall manufacturing process through pre-planned height control
Solution Approach 2:
The stop layer acts as an intermediary element between the first gate and the second gate, mediating the height difference relationship. This intermediary structure enables precise control of the second gate's bottom surface position relative to the first gate, facilitating reduced on-resistance while managing manufacturing complexity through a clear reference mechanism
Data Source
AI summary
Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first dielectric layer, a first gate, a second dielectric layer, and a second gate. The first dielectric layer is located on the substrate. The first gate is located on the first dielectric layer. The second dielectric layer is located on the substrate. The second gate is located on the second dielectric layer. A bottom surface of the second gate and a bottom surface of the first gate are located on different planes.